REL1.3
Page 22 of 80
RZ/G1M/G1N Qseven SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
2.6.10
DATA UART Interface
The RZ/G1M/G1N Qseven SOM supports two UART interface on Qseven Edge connector for Data UART interface and
Debug UART interface. RZ/G1M/G1N
CPU’s SCIF
B1 controller is used for Data UART interface with hardware flow
control for request to send and clear to send signals on Qseven Edge connector.
The RZ/G1M/G1N
CPU’s SCIFB1 supports
serial communication interface incorporating 256-byte transmit/receive
FIFOs that handles asynchronous communication. Serial data communications can be carried out with standard
asynchronous communications chips such as a Universal Asynchronous Receiver/Transmitter. It has On-chip baud rate
generator that allows any bit rate to be selected. Also it supports multibyte DMA transfers.
For more details, refer Qseven Edge connector pins 171, 172, 177 & 178 for Data UART interface on
2.6.11
CAN Interface
The RZ/G1M/G1N Qseven SOM supports one CAN interface on Qseven Edge connector along with one more CAN
interface on Expansion connector2. RZ/G1M/G1N
CPU’s
CAN module supports two channels in which CAN0 channel is
connected to Qseven Edge connector.
The RZ/G1M/G1N
CPU’s
CAN module complies with the ISO11898-1 Specifications and supports programmable bit
rate up to 1 Mbps with both formats of messages namely the standard identifier (11 bits) and extended ID (29 bits).It
also supports 64 mailboxes in two selectable mailbox mode Normal mailbox mode and FIFO mailbox mode. To connect
external CAN module to this bus, it is necessary to add transceiver in between.
For more details, refer Qseven Edge connector pins 129 & 130 on
2.6.12
SPI Interface
The RZ/G1M/G1N Qseven SOM supports one SPI interface with two chip selects on Qseven Edge connector.
RZ/G1M/G1N
CPU’s MSIOF2 is used for SPI interface which supports full
-duplex synchronous four-wire serial interface
with DMA.
The RZ/G1M/G1N
CPU’s
MSIOF2 supports serial formats IIS, SPI (master and slave modes) at max speed of 26Mbps. It
supports 32bit x 64 stages for transmit FIFOs & 32bit × 256 stages for receive FIFOs and allows MSB first or LSB first
selectable for data transmission and reception.
For more details, refer Qseven Edge connector pins 199 to 203 on