REL1.3
Page 53 of 80
RZ/G1M/G1N Qseven SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
Pin
No
Signal Name
CPU Ball Name/
Pin Number
Signal Type/
Termination
Description
79
SCIF1_RX1(GP2_25)
SSI_SCK9/
AB31
I, 3.3V CMOS
Serial Communication Interface
(SCIF1) Serial Data Receiver.
80
DU1_DOTCLKIN(GP3_24)
DU1_DOTCLKIN/
AL9
I, 3.3V CMOS
DU1 dot clock input.
Note: MLBP_DAT_N is optionally
connected to this pin through
resistor and default not populated.
¹ Important Note: These signals are also used for RZ/G1M/G1N CPU bootstrap setting on SOM and so no external loads
or pull-up/pull-down resistors to be connected to these pins which will change the boot configuration.
