REL1.3
Page 60 of 80
RZ/G1M/G1N Qseven SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
Interface/
Function
Qseven
Edge
Pin Number
RZ/G1M/G1N
CPU
Pin Number
Function 1
Function 2
Function 3
Function 4
Function 5
Function 6
Function 7
Function 8
GPIO
Default
State
PCIe
179
AL25
TODP1_SATA
TODP1_PCIe
TODP1_PCIe
181
AL26
TODN1_SATA
TODN1_ PCIe
TODN1_ PCIe
180
AL23
RIDP1_SATA
RIDP1_PCIe
RIDP1_PCIe
182
AL24
RIDN1_SATA
RIDN1_PCIe
RIDN1_PCIe
156
AK3
VI1_DATA6
AVB_MAGIC
GP5_11
GP5_11
158
AB28
IRQ9
DU1_DOTCLK
IN_B
CAN_CLK_D
SCIF_CLK_B
GP7_19
GP7_19
GPIO's
192
U31
HSCK1
SCIFB1_SCK
GP7_7
GP7_7
189
W31
SSI_SCK1
I2C0_SDA_B
IIC0_SDA_B
MSIOF2_SYN
C_C
GP2_3
GP2_3
185
Y31
SSI_SCK4
GP2_12
GP2_12
187
AA27
SSI_SCK78
GP2_21
GP2_21
191
W28
SSI_SDATA2
TX2_E
HRTS1#_E
GP2_8
GP2_8
186
AA29
SSI_SDATA6
VI1_R7_B
GP2_20
GP2_20
188
AA30
SSI_WS6
MSIOF2_SS2_
D
VI1_R6_B
GP2_19
GP2_19
190
V28
SSI_WS1
I2C1_SCL_B
IIC1_SCL_B
MSIOF2_TXD
_C
GP2_4
GP2_4
SPI
199
Y27
SSI_WS5
MSIOF1_SYN
C_C
TS_SCK0
MSIOF2_TXD
_D
VI1_R3_B
GP2_16
GP2_16
200
Y28
SSI_SCK5
MSIOF1_SCK
_C
TS_SDATA0
VI1_R6_B
MSIOF2_SYN
C_D
VI1_R2_B
GP2_15
GP2_15
201
AA31
SSI_SCK6
MSIOF1_RXD
_C
TS_SPSYNC0
MSIOF2_RXD
_D
VI1_R5_B
GP2_18
GP2_18
202
Y26
SSI_SDATA5
MSIOF1_TXD
_C
TS_SDEN0
MSIOF2_SS1_
D
VI1_R4_B
GP2_17
GP2_17
203
N1
EX_CS1#
MSIOF2_SCK
GP1_13
GP1_13
PWM
123
U4
DREQ0
PWM3
TPU_TO3
GP1_24
GP1_24
196
R31
DU1_DOTCLK
IN_C
AUDIO_CLKB
_B
PWM5_B
SCIFA3_RXD_
C
GP7_20
GP7_20
Debug UART
208
Y25
SSI_SDATA7
RX0_D
GP2_23
GP2_23
209
AA26
SSI_WS78
TX0_D
GP2_22
GP2_22