REL1.3
Page 33 of 80
RZ/G1M/G1N Qseven SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
Pin
No.
Qseven Edge
Connector
Pin Name
Signal Name
CPU Ball Name/
Pin Number
Signal Type/
Termination
Description
126
eDP0_HPD#
/LVDS_BLC_
DAT
NC
NA
-
Default NC.
Note:
GP2_7
is
optionally
connected to this pin (for
I2C2_SDA) through resistor and
default not populated.
127
GP2_I2C_CLK
/LVDS_DID_C
LK
NC
NA
-
Default NC.
Note:
GP2_6
is
optionally
connected to this pin (for
I2C2_SCL) through resistor and
default not populated.
128
eDP1_HPD#
/LVDS_BLC_
CLK
NC
NA
-
Default NC.
Note:
GP2_6
is
optionally
connected to this pin (for
I2C2_SCL) through resistor and
default not populated.
129
CAN0_TX
CAN0_TX(GP2_2
6)
SSI_WS9/
AB30
O, 3.3V CMOS
Transmit
output
for
CAN
Channel0.
130
CAN0_RX
CAN0_RX(GP2_
27)
SSI_SDATA9/
AB29
I, 3.3V CMOS
Receive input for CAN Channel0.
131
D/
T
NC
NA
-
NC.
132
RSVD
NC
NA
-
NC.
133
DP_LANE3-/
TMDS_CLK-
NC
NA
-
NC.
134
RSVD
NC
NA
-
NC.
135
GND
GND
NA
Power
Ground.
136
GND
GND
NA
Power
Ground.
137
D/
TMDS_LANE
1+
NC
NA
-
NC.
138
NC
NA
-
NC.
139
DP_LANE1-/
TMDS_LANE
1-
NC
NA
-
NC.
140
DP_AUX-
NC
NA
-
NC.
141
GND
GND
NA
Power
Ground.
142
GND
GND
NA
Power
Ground.
143
D/
TMDS_LANE
0+
NC
NA
-
NC.
144
RSVD
NC
NA
-
NC.
