REL1.3
Page 15 of 80
RZ/G1M/G1N Qseven SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
2.4
Memory
2.4.1
DDR3L SDRAM
The RZ/G1M/G1N Qseven SOM supports 1GB DDR3L RAM memory by default. This is connected to CPU in 32bit x 2ch
mode where it uses four 256MB DDR3L-SDRAM ICs. This device operates at 1.35V voltage level. DDR3L-SDRAM ICs are
physically located on either side of the SOM. The RAM size can be expandable up to maximum of 4GB. For customised
DDR3L memory based SOM contact iWave support team
Note: In RZ/G1N SOM, DDR3L-SDRAM is connected in 32bit x 1ch mode where it uses two 512MB DDR3L-SDRAM ICs
by default.
2.4.2
SPI NOR Flash
The RZ/G1M/G1N Qseven SOM supports 2MB SPI NOR Flash as default boot device. This is connected to QSPI
controller of the RZ/G1M/G1N CPU and operates at 3.3 Voltage level. While RZ/G1M/G1N booting, boot program in
the on-chip ROM starts up the QSPI and SYS-DMAC channel 1, and transfers the loader program previously stored in
the SPI Flash to the on-chip RAM via the QSPI controller. After loader program is transferred, the program
automatically jumps to the top address of the loader program. The SPI flash memory (U1) is physically located on top
side of the Qseven SOM.
Figure 3: SPI NOR Flash
