REL1.3
Page 36 of 80
RZ/G1M/G1N Qseven SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
Pin
No.
Qseven Edge
Connector
Pin Name
Signal Name
CPU Ball Name/
Pin Number
Signal Type/
Termination
Description
189
LPC_CLK/
GPIO4
Q7_GPIO4_(GP2
_3)
SSI_SCK1/
W31
IO, 3.3V CMOS
General purpose input/output 4.
190
LPC_FRAME#
/ GPIO5
Q7_GPIO5_(GP2
_4)
SSI_WS1/
V28
IO, 3.3V CMOS
General purpose input/output 5.
191
SERIRQ /
GPIO6
Q7_GPIO6_(GP2
_8)
SSI_SDATA2/
W28
IO, 3.3V CMOS
General purpose input/output 6.
192
LPC_LDRQ#/
GPIO7
Q7_GPIO7_(GP7
_7)
HSCK1/
U31
IO, 3.3V CMOS
General purpose input/output 7.
193
VCC_RTC
VRTC_3V0
NA
I, 3V Power
3V backup coin cell input for RTC.
194
SPKR/
GP_PWM_O
UT2
NC
NA
-
NC.
195
FAN_TACHOI
N/
GP_TIMER_I
N
NC
NA
-
NC.
196
FAN_PWMO
UT/
GP_PWM_O
UT1
PWM5(GP7_20) GPS_CLK/
R31
O, 3.3V CMOS
Pulse Width Modulated output 5.
197
GND
GND
NA
Power
Ground.
198
GND
GND
NA
Power
Ground.
199
SPI_MOSI
MSIOF2_TXD(G
P2_16)
SSI_WS5/
Y27
O, 3.3V CMOS
SPI Master serial output/Slave
serial input(MSIOF2).
200
SPI_CS0#
MSIOF2_SYNC(
GP2_15)
SSI_SCK5/
Y28
O, 3.3V CMOS
SPI frame synchronization signal
(MSIOF2).
201
SPI_MISO
MSIOF2_RXD(G
P2_18)
SSI_SCK6/
AA31
I, 3.3V CMOS
SPI Master serial input /Slave
serial output (MSIOF2).
202
SPI_CS1#
MSIOF2_SS1(GP
2_17)
SSI_SDATA5/
Y26
O, 3.3V CMOS
SPI frame synchronization signal1
(MSIOF2).
203
SPI_SCK
MSIOF2_SCK(GP
1_13)
EX_CS1#/
N1
O, 3.3V CMOS
SPI Serial clock (MSIOF2).
204
MFG_NC4
NC
NA
-
Default NC.
Note: Optionally CPU TRST# pin is
connected to this pin through 1.8V
to 3.3V level translator and
default not populated.
205
VCC_5V_SB
NC
NA
-
NC.
206
VCC_5V_SB
NC
NA
-
NC.
