REL1.3
Page 55 of 80
RZ/G1M/G1N Qseven SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
Table 8: JTAG Header Pin Assignment
Pin
No
Signal Name
Signal Type/
Termination
Description
1
VCC_1V8
O, 1.8V Power
VTREF Voltage Reference.
2
VCC_1V8
O, 1.8V Power
Supply Voltage.
3
JTAG_TRSTB
I, 1.8V CMOS/
4.7K PD
JTAG test reset signal.
4
GND
Power
Ground.
5
JTAG_TDI
I, 1.8V CMOS/
4.7K PU
JTAG test data input.
6
GND
Power
Ground.
7
JTAG_TMS
I, 1.8V CMOS/
4.7K PU
JTAG test mode select.
8
GND
Power
Ground.
9
JTAG_TCK
I, 1.8V CMOS/
4,7K PU
JTAG test Clock.
10
GND
Power
Ground.
11
-
I, 1.8V CMOS/
10K PD
Only pull down is provided.
12
GND
Power
Ground.
13
JTAG_TDO
O, 1.8V CMOS
JTAG test data output.
14
GND
Power
Ground.
15
JTAG_RESETB
I, 1.8V CMOS/
4,7K PU
Reset input.
16
GND
Power
Ground.
17
-
I, 1.8V CMOS/
4,7K PU
Only pull up is provided.
18
GND
Power
Ground.
19
-
-
Default NC.
Note: Optionally this pin is connected to CPU ACK
pin (AE17) through resistor and default not
populated.
20
GND
Power
Ground.
