REL1.3
Page 11 of 80
RZ/G1M/G1N Qseven SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
2.
ARCHITECTURE AND DESIGN
This section provides detailed information about the RZ/G1M/G1N Qseven SOM features and Hardware architecture
with high level block diagram. Also this section provides detailed information about Qseven edge connector &
Expansion connector’s pin assignment
and usage.
2.1
RZ/G1M/G1N QsevenSOM Block Diagram
iW-RainboW-G20M - RZ/G1M, RZ/G1N Qseven SOM Block Diagram
¹ PCIe is supported by default. SATA1 is not supported by default.
² USB3.0 is supported by default. SATA0 is not supported by default.
³ SCIF4 cannot be supported If VI1 16bit camera is used.
CPU
RZ/G1M,
RZ/G1N
DDR3L -1GB
(Upgradable)
SPI Flash - 2MB
(Upgradable)
eMMC - 4GB
(Upgradable)
QSEVEN
PCB Edge
Connector
(230Pin)
USB3.0 x 1
²
LVDS x 1
Gigabit
Ethernet
GMII x 1
SDHC (4bit) x 1
I2C x 2
SPI x 1 (2 Chip selects)
CAN x 1
8 GPIOs, Status & Control Signals
PCIe/
SATA1
USB3.0/
SATA0
LVDS-DU0
EtherAVB
SDHI2
I2C2,
I2C5
MSIOF2
CAN0
GPIOs
MMC (8bit)
SPI
DDR3 (32bit)
Micro SD
Connector
SD (4bit)
Expansion
Connector1
(80Pin header)
Gigabit
Ethernet PHY
DBSC3
–
CH0
QSPI
MMC/
SDHI3
SDHI0
I2S x 1
SSI0/
SSI1
SCIF0
LCD (24bpp) x 1 & Camera (8bit) x 1
(or) Camera (16bit) x 1
DU1,
VI1
SSI3/
SSI4
LBSC
SSI/I2S x 1
JTAG
Memory Bus (16bit Sync/Async)
UART x 1
2Pin Power In
(Optional)
JTAG
Power to
Peripherals
5V
Debug
VI0,VI2
Camera (24bit) x 1 (or) Camera (8bit) x 2
JTAG
(20 Pin Header)
On-Board
Regulators
Dual SPDT
Switch IC
(Optional)
Expansion
Connector2
(80Pin header)
MSIOF1/
HSCIF1
SPI x 1 (or) UART (with CTS & RTS) x 1
CAN1
CAN x 1
DDR3 (32bit)
DBSC3
–
CH1
PWM x 2
PWM3,
PWM5
UART (with CTS & RTS) x 1
SCIFB1
USB1
SCIF1
UART x 1
PWM x 1
PWM1
SCIF4
³
UART x 1
USB2.0 HUB
(2 Ports)
USB Host x 2
USB OTG
USB2.0 OTG x 1
USB0
RTC Controller
I2C2
SPI
Programming
Header
PCIe x 1
¹
SATA x 1
¹
VRTC
VRTC
Note: Green Font blocks are not supported in RZ/G1N CPU
Figure 1: RZ/G1M/G1N Qseven SOM Block Diagram
