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REL1.3

Page 44 of 80

RZ/G1M/G1N Qseven SOM Hardware User Guide

iWave Systems Technologies Pvt. Ltd.

Pin

Signal Name

CPU Ball Name/

Pin Number

Signal Type/
Termination

Description

DU1_DG4/VI1_DATA6_B(GP
3_12)

DU1_DG4/
AG11

O, 3.3V CMOS

Display Unit Channel1 Green data
bit4 (or) Video Input Channel1 data
bit6 (GroupB).

VI0_R2/VI2_DATA3(GP4_23) VI0_R2/

AE4

I, 3.3V CMOS

Video Input Channel2 data bit3 (or)
Video Input Channel0 red data bit2.

DU1_DG3/VI1_DATA5_B(GP
3_11)

DU1_DG3/
AH11

O, 3.3V CMOS

Display Unit Channel1 Green data
bit3 (or) Video Input Channel1 data
bit5 (GroupB).

VI0_R1/VI2_DATA2(GP4_22) VI0_R1/

AE3

I, 3.3V CMOS

Video Input Channel2 data bit2 (or)
Video Input Channel0 red data bit1.

DU1_DG2/VI1_DATA4_B(GP
3_10)

DU1_DG2/
AJ11

O, 3.3V CMOS

Display Unit Channel1 Green data
bit2 (or) Video Input Channel1 data
bit4 (GroupB).

VI0_R0/VI2_DATA1(GP4_21) VI0_R0/

AE1

I, 3.3V CMOS

Video Input Channel2 data bit1 (or)
Video Input Channel0 red data bit0.

DU1_DG1/VI1_DATA3_B(GP
3_9)

DU1_DG1/
AK11

O, 3.3V CMOS

Display Unit Channel1 Green data
bit1 (or) Video Input Channel1 data
bit3 (GroupB).

GND

Power

Ground.

DU1_DG0/VI1_DATA2_B(GP
3_8)

DU1_DG0/
AL11

O, 3.3V CMOS

Display Unit Channel1 Green data
bit0 (or) Video Input Channel1 data
bit2 (GroupB).

VI0_CLK(GP4_0)

VI0_CLK/
AC1

I, 3.3V CMOS

Video Input Channel0 pixel clock.

GND

Power

Ground.

VI1_CLKENB_C/VI1_G1_B(G
P6_25)

MSIOF0_SYNC/
T30

I, 3.3V CMOS

Video Input Channel1 Data enable
signal (GroupC) (or) Video Input
Channel1 green data bit1 (GroupB).

Note: GP4_1 is optionally connected
(for VI0_CLKENB) to this pin through
resistor and default not populated.

DU1_DR1/VI1_DATA1_B(GP
3_1)

DU1_DR1/
AK12

O, 3.3V CMOS

Display Unit Channel1 Red data bit1
(or) Video Input Channel1 data bit1
(GroupB).

VI0_HSYNC#(GP4_3)

VI0_HSYNC#/
AB2

I, 3.3V CMOS

Video Input Channel0 Horizontal
sync signal.

DU1_DR0/VI1_DATA0_B(GP
3_0)

DU1_DR0/
AL12

O, 3.3V CMOS

Display Unit Channel1 Red data bit0
(or) Video Input Channel1 data bit0
(GroupB).

VI1_FIELD_C/VI1_G2_B(GP6
_26)

MSIOF0_TXD/
T29

I, 3.3V CMOS

Video Input Channel1 Field signal
(GroupC) (or) Video Input Channel1
green data bit2 (GroupB).

Summary of Contents for iW-RainboW-G20M

Page 1: ...REL1 3 Page 1 of 80 RZ G1M G1N Qseven SOM Hardware User Guide iWave Systems Technologies Pvt Ltd iW RainboW G20M RZ G1M RZ G1N Qseven SOM Hardware User Guide...

Page 2: ...58 Orderble Part Number is updated in Table 18 Non substantive changes throughout the document 1 2 18th Nov 2016 Section 2 4 2 Section 2 6 1 and Table 4 are updated Section 2 12 is newly added Non sub...

Page 3: ...errata and associated issues Trademarks All registered trademarks product names mentioned in this publication are the property of their respective owners and used for identification purposes only Cert...

Page 4: ...16 2 6 Qseven PCB Edge Connector 17 2 6 1 Gigabit Ethernet 18 2 6 2 USB3 0 Host Interface 18 2 6 3 PCIe Interface 19 2 6 4 SATA Interface Optional 19 2 6 5 USB 2 0 OTG Interface 20 2 6 6 USB 2 0 Host...

Page 5: ...PinMultiplexing on Qseven Edge and Expansion Connectors 58 2 12 RZ G1M CPU Reference Schematic 65 3 TECHNICAL SPECIFICATION 70 3 1 Electrical Characteristics 70 3 1 1 Power Input Requirement 70 3 1 2...

Page 6: ...76 Figure 16 Qseven Module Insertion procedure 77 Figure 17 RZ G1M G1N Qseven SOM Development Platform with Add on Module 79 List of Tables Table 1 Acronyms Abbreviations 7 Table 2 Terminology 9 Tabl...

Page 7: ...oard Qseven modules have a standardized form factor of 70mm x 70mm and have specified pin outs based on the high speed MXM system connector that has a standardized pin out regardless of the vendor A s...

Page 8: ...lock Synchronized Serial Interface with FIFO PCB Printed Circuit Board PWM Pulse Width Modulation QSPI Quad Serial Peripheral Interface RTC Real Time Clock SCIF Serial Communication Interface with FIF...

Page 9: ...ry Metal Oxide Semiconductor Signal DIFF Differential Signal LVDS Low Voltage Differential Signal OD Open Drain Signal OC Open Collector Signal Power Power Pin PU Pull Up PD Pull Down NA Not Applicabl...

Page 10: ...Function Name GPIO Number Example MSIOF2_SCK GP1_13 In this signal MSIOF2_SCK is the functionality which we are using and GP1_13 is the GPIO number If CPU pin has multiplexing option and selected as G...

Page 11: ...C x 2 SPI x 1 2 Chip selects CAN x 1 8 GPIOs Status Control Signals PCIe SATA1 USB3 0 SATA0 LVDS DU0 EtherAVB SDHI2 I2C2 I2C5 MSIOF2 CAN0 GPIOs MMC 8bit SPI DDR3 32bit Micro SD Connector SD 4bit Expan...

Page 12: ...tures Gigabit Ethernet PHY Transceiver USB 2 0 High Speed 2 Port Hub RTC controller JTAG Header SPI Programming Header Qseven PCB Edge Interfaces Gigabit Ethernet x 1 Port through On SOM Gigabit Ether...

Page 13: ...supported 3 In RZ G1N CPU USB3 0 PCIe SATA are multiplexed in same pins and so either one interface only can be used at a time By default USB3 0 is supported 4 In RZ G1M G1N CPU DU1 VIN1 some pins ar...

Page 14: ...G1N CPU with built in dual ARM Cortex A15 Microprocessor core which can operate up to 1 5 GHz core The Block Diagram of RZ G1M CPU from Renesas s website is shown below for reference Figure 2 RZ G1M S...

Page 15: ...RZ G1N SOM DDR3L SDRAM is connected in 32bit x 1ch mode where it uses two 512MB DDR3L SDRAM ICs by default 2 4 2 SPI NOR Flash The RZ G1M G1N Qseven SOM supports 2MB SPI NOR Flash as default boot devi...

Page 16: ...11 The main power to Micro SD Card Connector is 3 3 Voltage The RZ G1M G1N Qseven SOM optionally supports configurable IO voltage levels for SDHI0 lines which can be controlled through CPU GPIO GP1_13...

Page 17: ...s per Qseven Specification 2 0 The interfaces which are available at 230pin Qseven Edge connector J5 are explained in the following sections Figure 5 Qseven PCB Edge Connector Number of Pins 230 Conne...

Page 18: ...net Discrete Transformer HX5008NL Pulse 40 C to 85 C Gigabit Ethernet Discrete Transformer 000 7093 37R LF1 Wurth 0 C to 70 C RJ45 Magjack with two Green LED JK0654219NL Pulse 0 C to 70 C RJ45 Magjack...

Page 19: ...e pins and so either one interface only can be used at a time By default USB3 0 is supported Please contact iWave if PCIe or SATA support is required in RZ G1N CPU based Qseven SOM 2 6 4 SATA Interfac...

Page 20: ...Host controller with integrated PHY which supports USB2 0 High Speed 480 Mbps Full Speed 12 Mbps Low Speed 1 5 Mbps transfer Two port USB hub Outputs are connected to Qseven Edge connector USB Port0 a...

Page 21: ...f Qseven Edge connector LVDS panel power enable and LVDS panel backlight enable output are supported on Qseven Edge connector from RZ G1M G1N CPU GPIOs GP7_25 and GP5_14 correspondingly Also LVDS pane...

Page 22: ...along with one more CAN interface on Expansion connector2 RZ G1M G1N CPU s CAN module supports two channels in which CAN0 channel is connected to Qseven Edge connector The RZ G1M G1N CPU s CAN module...

Page 23: ...interface This PWM timer has a 10 bit counter and supports configurable PWM output cycle within the range from 2 cycles to 224 1024 cycles of internal bus clock i e from 30 77 ns to 264 seconds when...

Page 24: ..._RTC coin cell power input from Qseven Edge connector to RTC controller for real time clock when VCC is off RZ G1M Qseven SOM doesn t use Standby power supply from Qseven Edge connector For more detai...

Page 25: ...nector 8th 13th pins through resistors and default populated So use only in one place 8 GBE_LINK10 00 GPHY_LINK_LED 2 NA O 3 3V CMOS 4 7K PD Gigabit Ethernet link status LED Note Same signal is also c...

Page 26: ...p with 10K directly 20 PWRBTN NC NA NC 21 SLP_BTN NC NA NC 22 LID_BTN NC NA NC 23 GND GND NA Power Ground 24 GND GND NA Power Ground 25 GND GND NA Power Ground 26 PWGIN PWRGIN NA I 5V CMOS Active high...

Page 27: ...01uF AC Coupling Capacitor and default not populated 36 SATA1_RX NC NA NC 37 SATA0_RX NC NA Default NC Note RIDN0_SATA RIDN1_SATA is optionally connected to this pin for SATA_RXN through 0 01uF AC Cou...

Page 28: ...O_DAT7 NC NA NC 55 SDIO_DAT6 NC NA NC 56 USB_DRIVE_ VBUS USB0_PWEN GP 7_23 USB0_PWEN AF31 O 3 3V CMOS Power Enable Control output for USB0 OTG VBUS 57 GND GND NA Power Ground 58 GND GND NA Power Groun...

Page 29: ...not populated 69 THRM NC NA NC 70 WDTRIG NC NA NC 71 THRMTRIP GPIO_THRMTRI P_Q7 GP5_31 SPEEDIN T25 O 3 3V CMOS 10K PU Thermal Trip Note GP5_31 is connected to this pin as GPIO for implementing Therma...

Page 30: ...OM USB Hub OCS1 pin 87 USB_P3 NC NA NC 88 USB_P2 USB_HUB2OUT _DM NA IO DIFF USB Host port2 data negative Note This pin is connected from On SOM USB Hub USBDM_DN2 pin 89 USB_P3 NC NA NC 90 USB_P2 USB_H...

Page 31: ...U0_LVDS_CH0_N AJ22 O 1 8V LVDS LVDS primary channel differential pair0 negative 102 eDP1_TX0 LVDS_B0 NC NA NC 103 eDP0_TX1 LVDS_A1 DU0_LVDS_CH1 _P DU0_LVDS_CH1_P AL21 O 1 8V LVDS LVDS primary channel...

Page 32: ...VDS primary channel differential pair3 negative 116 eDP1_TX3 LVDS_B3 NC NA NC 117 GND GND NA Power Ground 118 GND GND NA Power Ground 119 eDP0_AUX LVDS_A_CLK DU0_LVDS_CLK _P DU0_LVDS_CLK_P AE20 O 1 8V...

Page 33: ...pulated 128 eDP1_HPD LVDS_BLC_ CLK NC NA Default NC Note GP2_6 is optionally connected to this pin for I2C2_SCL through resistor and default not populated 129 CAN0_TX CAN0_TX GP2_2 6 SSI_WS9 AB30 O 3...

Page 34: ...Ie differential reference clock positive from 100Mhz oscillator 156 PCIE_WAKE GPIO_PCIe_WA KE GP5_11 VI1_DATA6 AK3 I 3 3V CMOS PCIe wake event Note GP5_11 is connected to this pin as GPIO for implemen...

Page 35: ...tion Interface SCIFB1 Serial Data Receiver 178 UART0_CTS SCIFB1_CTS GP 7_8 HCTS1 U29 I 3 3V CMOS Serial Communication Interface SCIFB1 ready to send handshake signal 179 PCIE0_TX PCIe1_TXP TODP1_SATA...

Page 36: ...NC 195 FAN_TACHOI N GP_TIMER_I N NC NA NC 196 FAN_PWMO UT GP_PWM_O UT1 PWM5 GP7_20 GPS_CLK R31 O 3 3V CMOS Pulse Width Modulated output 5 197 GND GND NA Power Ground 198 GND GND NA Power Ground 199 SP...

Page 37: ...Optionally CPU TMS pin is connected to this pin through 1 8V to 3 3V level translator and default not populated 211 VCC VCC_5V NA I 5V Power Supply Voltage 212 VCC VCC_5V NA I 5V Power Supply Voltage...

Page 38: ...effort has been made in RZ G1M G1N Qseven SOM design to provide maximum interfaces of RZ G1M G1N CPU to the carrier board by adding two 80Pin Expansion connectors The interfaces which are available at...

Page 39: ...version function from RGB to ARGB For more details refer Expansion connector1 pins on Table 6 Table 5 Parallel Camera Interface Pin Assignment on Expansion connector1 RZ G1M G1N VIN Channel VIN Channe...

Page 40: ...Table 6 Note In RZ G1M G1N CPU DU1 VIN1 some pins are multiplexed in same pins and so DU1 cannot be supported when VIN1 is supported in 16bit mode If VIN1 is supported in 8bit mode then DU1 also can...

Page 41: ...t Channel0 blue data bit7 8 VI1_DATA5 GP7_4 HTX0 P30 I 3 3V CMOS Video Input Channel1 data bit5 9 VI0_B6 VI0_DATA6 GP4_11 VI0_DATA6 VI0_B6 AC6 I 3 3V CMOS Video Input Channel0 data bit6 or Video Input...

Page 42: ...bit4 GroupB 23 GND NA Power Ground 24 VI1_CLK_C VI1_G0_B GP6_2 4 MSIOF0_SCK T31 I 3 3V CMOS Video Input Channel1 pixel clock GroupC or Video Input Channel1 green data bit0 GroupB 25 VI0_G7 VI2_DATA0...

Page 43: ...DB1 AH9 O 3 3V CMOS Display Unit Channel1 Blue data bit1 or Video Input Channel1 Horizontal sync signal GroupB 41 GND NA Power Ground 42 DU1_DB0 VI1_CLK_B GP3_1 6 DU1_DB0 AJ9 O 3 3V CMOS Display Unit...

Page 44: ...U1_DG1 VI1_DATA3_B GP 3_9 DU1_DG1 AK11 O 3 3V CMOS Display Unit Channel1 Green data bit1 or Video Input Channel1 data bit3 GroupB 59 GND NA Power Ground 60 DU1_DG0 VI1_DATA2_B GP 3_8 DU1_DG0 AL11 O 3...

Page 45: ...respectively 72 DU1_DR5 GP3_5 DU1_DR5 AF12 O 3 3V CMOS Display Unit Channel1 Red data bit5 73 DU1_VSYNC GP3_28 MD2 1 DU1_EXVSYNC DU 1_VSYNC AF8 O 3 3V CMOS 100K PU Display Unit Channel1 Vertical sync...

Page 46: ...en SOM supports Expansion connector2 also to pull out more interfaces of RZ G1M G1N CPU The interfaces which are available at 80pin Expansionconnector2 are explained in the following sections Figure 7...

Page 47: ...module complies with the ISO11898 1 Specifications and supports programmable bit rate up to 1 Mbps with both formats of messages namely the standard identifier 11 bits and extended ID 29 bits It also...

Page 48: ...upported with Hardware flow control signals If HSCIF1is supported without Hardware flow control signals then MSIOF1 also can be supported 2 8 5 PWM Interface The RZ G1M G1N Qseven SOM supports one PWM...

Page 49: ...te Controller Address bit16 9 LBSC_D13 D13 Y1 IO 3 3V CMOS Low Bus State Controller Data bit13 10 LBSC_A12 A12 T2 O 3 3V CMOS Low Bus State Controller Address bit12 11 LBSC_D5 D5 AA2 IO 3 3V CMOS Low...

Page 50: ...IO 3 3V CMOS Low Bus State Controller Data bit0 32 LBSC_A141 A14 MD19 R6 O 3 3V CMOS 10K PD Low Bus State Controller Address bit14 33 GND NA Power Ground 34 GND NA Power Ground 35 LBSC_D7 D7 Y7 IO 3 3...

Page 51: ...el 3 and channel 4 53 EX_WAIT0 GP1_23 EX_WAIT0 U3 I 3 3V CMOS Low Bus State Controller wait state insertion pin 54 SSI_SDATA3 GP2_11 SSI_SDATA3 W25 IO 3 3V CMOS Audio Serial data for channel 3 55 WE0...

Page 52: ...GP2_29 AUDIO_CLKB AC30 IO 3 3V CMOS SPI serial clock 70 NMI NMI AL16 I 3 3V CMOS 10K PU External Non maskable Interrupt Note MLBP_SIG_N is optionally connected to this pin through resistor and default...

Page 53: ...Communication Interface SCIF1 Serial Data Receiver 80 DU1_DOTCLKIN GP3_24 DU1_DOTCLKIN AL9 I 3 3V CMOS DU1 dot clock input Note MLBP_DAT_N is optionally connected to this pin through resistor and defa...

Page 54: ...in ARM JTAG connector J3 is available in SOM for JTAG interface Even though this JTAG connector pinout is fully compatible with ARM JTAG 20 connector the physical dimension of connector is made smalle...

Page 55: ...AG test data input 6 GND Power Ground 7 JTAG_TMS I 1 8V CMOS 4 7K PU JTAG test mode select 8 GND Power Ground 9 JTAG_TCK I 1 8V CMOS 4 7K PU JTAG test Clock 10 GND Power Ground 11 I 1 8V CMOS 10K PD O...

Page 56: ...ionally JTAG debugger through JTAG Header J4 Optionally the external SPI programmer with 8pin SOIC test clips Example part 923655 08 from 3M can be used for programming the SPI Flash Figure 9 SPI Flas...

Page 57: ...nally SOM can be powered up using Power IN Header P1 for standalone purpose This is the optional feature and will not be populated in default configuration Figure 10 2Pin Power Connector Table 10 Powe...

Page 58: ...n Edge Connector interfaces Interface Function Qseven Edge Pin Number RZ G1M G1N CPU Pin Number Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Function 7 Function 8 GPIO Default Sta...

Page 59: ...LVDS_C LK_P 121 AF20 DU0_LVDS_C LK_N DU0_LVDS_C LK_N 99 AJ23 DU0_LVDS_C H0_P DU0_LVDS_C H0_P 101 AJ22 DU0_LVDS_C H0_N DU0_LVDS_C H0_N 103 AL21 DU0_LVDS_C H1_P DU0_LVDS_C H1_P 105 AL22 DU0_LVDS_C H1_N...

Page 60: ...GP2_3 GP2_3 185 Y31 SSI_SCK4 GP2_12 GP2_12 187 AA27 SSI_SCK78 GP2_21 GP2_21 191 W28 SSI_SDATA2 TX2_E HRTS1 _E GP2_8 GP2_8 186 AA29 SSI_SDATA6 VI1_R7_B GP2_20 GP2_20 188 AA30 SSI_WS6 MSIOF2_SS2_ D VI1_...

Page 61: ...DATA6_B HRX0_B SCIFB2_RXD_B SSI_SDATA7_B GP3_12 GP3_12 54 AH11 DU1_DG3 VI1_DATA5_B SSI_WS78_B GP3_11 GP3_11 56 AJ11 DU1_DG2 VI1_DATA4_B SCIF1_SCK_B SCIFA1_SCK SSI_SCK78_B GP3_10 GP3_10 58 AK11 DU1_DG1...

Page 62: ...VI1_DATA1_C GP7_0 GP7_0 18 T28 MSIOF0_RXD VI1_DATA0_C VI1_G3_B GP6_27 GP6_27 20 T26 MSIOF0_SS2 MMC_D7 SCIF0_RX0_E VI1_VSYNC _C IIC0_SDA_C VI1_G5_B GP6_29 GP6_29 22 T27 MSIOF0_SS1 MMC_D6 SCIF0_TX0_E V...

Page 63: ...IF1_TX1_D GP2_24 GP2_24 79 AB31 SSI_SCK9 SCIF1_RX1_D GP2_25 GP2_25 HSCIF 62 AC28 IRQ5 HSCIF1_HTX1_C I2C1_SCL_E MSIOF2_SCK_E HSCIF1_HTX1_E GP7_15 GP7_15 64 AC29 IRQ4 HSCIF1_HRX1_C I2C4_SDA_C MSIOF2_RXD...

Page 64: ..._D GP0_26 GP0_26 31 AA7 LBSC_D0 GP0_0 GP0_0 32 R6 LBSC_A14 ATADIR0 _C MSIOF1_SYNC_D GP0_30 GP0_30 35 Y7 LBSC_D7 GP0_7 GP0_7 36 P7 LBSC_A19 DACK1 SCIFA1_TXD_C SCIFB1_TXD_C SCIFB1_SCK_B GP1_3 GP1_3 37 V...

Page 65: ...Hardware User Guide iWave Systems Technologies Pvt Ltd 2 12 RZ G1M CPU Reference Schematic RZ G1M CPU and DDR3 reference schematic is provided below Important Note This schematic is provided only for...

Page 66: ...REL1 3 Page 66 of 80 RZ G1M G1N Qseven SOM Hardware User Guide iWave Systems Technologies Pvt Ltd...

Page 67: ...REL1 3 Page 67 of 80 RZ G1M G1N Qseven SOM Hardware User Guide iWave Systems Technologies Pvt Ltd...

Page 68: ...REL1 3 Page 68 of 80 RZ G1M G1N Qseven SOM Hardware User Guide iWave Systems Technologies Pvt Ltd...

Page 69: ...REL1 3 Page 69 of 80 RZ G1M G1N Qseven SOM Hardware User Guide iWave Systems Technologies Pvt Ltd...

Page 70: ...ent of RZ G1M G1N Qseven SOM Table 14 Power Input Requirement Sl No Power Rail Min V Typical V Max V Max Input Ripple 1 VCC 4 75V 5V 5 25V 50mV 2 VCC_5V_SB NC NC NC NC 3 VCC_RTC3 2 8V 3V 3 3V 20 mV RZ...

Page 71: ...from Qseven Edge must be active at the same time or after VCC comes up Power down Sequence PWGIN signal from Qseven Edge must be inactive at the same time or before VCC goes down VCC must go down at t...

Page 72: ...0 95A 3 135W Dhrystone benchmark application VCC 1 0A 3 3W 1080p video playback on HDMI VCC 1 08A 3 564W Typical Maximum Power Audio playback on SSI0 SSI1 1080p video playback on LVDS0 EtherAVB 1000M...

Page 73: ...Z G1M G1N Qseven SOM operating temperature range is 25 C to 85 C 3 For more information on Thermal solution Heat spreader refer the following section 3 2 2 Heat Spreader For any highly integrated Syst...

Page 74: ...Compliance iWave s RZ G1M G1N Qseven SOM is designed by using RoHS compliant components and manufactured on lead free production process 3 2 4 Electrostatic Discharge iWave s RZ G1M G1N Qseven SOM is...

Page 75: ...specification Revision 2 0 The size of the PCB is 70mm x 70mm x 1 2mm as per Qseven Specification Qseven SOM mechanical dimension is shown below Please refer the Qseven Specification Revision 2 0 for...

Page 76: ...or L1 3 10mm 0 15mm and bottom side maximum height component is expansion connector 4 20mm 0 15mm followed by bulk capacitors 1 5mm 0 15mm Please refer the below figure which gives height details of t...

Page 77: ...off Insert the Qseven module in to the MXM connector at an angle of 30 as shown below in the first photo Check the Notch position of Qseven module is proper while inserting Once the Qseven module is i...

Page 78: ...L RZ G1M PF CPU 1GB DDR3 8GB eMMC exp connectors with boot code USB3 0 SATA Industrial iW G20M Q702 3D001G E008G BIP RZ G1M PF CPU 1GB DDR3 8GB eMMC exp connectors with boot code SATA PCIe Industrial...

Page 79: ...mm size the carrier board is highly packed with all necessary interfaces on board connectors to validate complete Qseven supported features iWave Systems supports also supports Camera Add On module fo...

Page 80: ...REL1 3 Page 80 of 80 RZ G1M G1N Qseven SOM Hardware User Guide iWave Systems Technologies Pvt Ltd...

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