Infineon Technologies C166S V2, User Manual

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User Manual
C166S V2
External Bus Controller
User Manual 6-169 V 1.7, 2001-01
6.3.7 EBC Idle State
When the external bus interface is enabled, but no external access is currently executed,
the EBC is idle. As long as only internal resources (from a CPU point of view) like RAM,
peripherals or registers, etc. are used, the external bus interface remains unchanged
(see
Table 6-3 ). The external control signals (RD and WR or WRL/WRH if enabled)
remain inactive (high).
6.4 Multi Master Systems
6.4.1 External Bus Arbitration
The C166S V2 supports multi master systems on the external bus by its external bus
arbitration. This bus arbitration allows an external master to request the C166S V2’s bus.
The C166S V2 will release the external bus and will float the data and address bus lines
and force the control signals via pull ups/downs to their inactive state.
6.4.1.1 Initialization of Arbitration
During reset all arbitration pins are tristate, except pin BREQ which is pulled inactive.
After reset the C166S V2 EBC always starts in ‘init mode’ where the external bus is
available but no arbitration is enabled. All arbitration pins are ignored in this state. Other
to the external bus connected C166S V2 EBCs assume to have the bus also, so
potential bus conflicts are not resolved. For a multimaster system the arbitration should
be initialized first before starting any bus access. The EBC can either be chosen as
arbitration master or as arbitration slave by programming the EBCMOD0 bit SLAVE. The
selected mode and the arbitration gets active by the first setting of the HLDEN bit inside
the CPUs PSW register. Afterwards a change of the slave/master mode is not possible
Table 6-3 Status of the External Bus Interface during EBC Idle State
Pins Internal accesses only
AD15 to AD0 Tristate (floating)
A15 to A0 Undefined address (if used for the bus interface)
A23 to A16 Undefined segment address (on selected pins)
CS7 to CS0 Inactive (high)
BHE Level corresponding to last external access
ALE Inactive (low)
RD Inactive (high)
WR/WRL Inactive (high)
WRH Inactive (high)