Infineon Technologies C166S V2, User Manual

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User Manual
C166S V2
Central Processing Unit
User Manual 2-79 V 1.7, 2001-01
Figure 2-21 Functional MAC Unit Block Diagram
The working register of the MAC Unit is a dedicated 40-bit wide Accumulator register. A
set of consistent flags is automatically updated in the MSW register (see
Section 2.7.10 )
after each MAC operation. These flags allow branching on specific conditions. Unlike the
PSW flags, these flags are not preserved automatically by the CPU upon entry into an
interrupt or trap routine. All dedicated MAC registers must be saved on the stack if the
MAC unit is shared between different tasks and interrupts.
2.7.1 Representation of Numbers and Rounding
The C166S V2 CPU supports the 2s complement representation of binary numbers. In
this format, the sign bit is the MSB of the binary word. This is set to zero for positive
numbers and set to one for negative numbers. Unsigned numbers are supported only by
multiply/multiply-accumulate instructions which specify whether each operand is signed
or unsigned.
In 2s complement fractional format, the N-bit operand is represented using the 1.[N-1]
format (1 signed bit, N-1 fractional bits). Such a format can represent numbers between
-1 and +1-2
-[N-1]
. This format is supported when MP of MCW is set.
Round+Saturation
40-bit Adder/Subtracter
Signed
Ext.
40-bit Signed Accumulator
ACCU-Shifter
16-bit input operands
signed/unsigned
Multiplier
Concatenation
Unit
Repeat Counter
MCW Register
MSW Register
Limiter
16-bit
32-bit
40-bit