Infineon Technologies C166S V2, User Manual

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User Manual
C166S V2
Introduction
User Manual 1-12 V 1.7, 2001-01
– Overlapping 8-bit and 16-bit registers
Multiply Accumulate Unit (MAC)
– Single cycle MAC with zero cycle latency including a 16*16 multiplier plus 40-bit barrel
shifter; single clock multiplication is ten times faster than C166 at the same CPU clock
– 40-bit accumulator to handle overflows
– Automatic saturation to 32 bit or rounding included with the MAC instruction
– Fractional numbers supported directly
– One Finite Impulse Response Filter (FIR) tap per cycle with no circular buffer
management
1.2.2 On-Chip Memory Modules
– Up to 3 KBytes on-chip dual ported SRAM for DSP data and register banks
– Up to 24 KBytes on-chip internal single ported SRAM module for data storage
– Up to 4 MBytes on-chip memory module for program storage
Note: The on-chip memory configuration may differ from product to product. Product
specific on-chip memory configurations are defined in the corresponding product
specifications.
1.2.3 Data Management Unit (DMU)
The Data Management Unit (DMU) handles all data transfers external to the core (i.e.
external memory or on-chip special function registers on the PDBUS+) and instruction
fetches in external memory. The DMU acts as a data mover between the various
interfaces. By handling all these interfaces, it incorporates the C166S V2 System Bus.
An access prioritization between
E xternal B US C ontroller (EBC) accesses from the core
and
P rogram M emory U nit (
PMU) is handled by the DMU. This allows an instruction
fetch from external memory in parallel with data access that is not on EBC.
1.2.4 Program Memory Unit (PMU)
The PMU has two basic functions: to provide the CPU with instructions and to provide
the CPU (through the DMU) with data located in the Internal Program Memory. The
Internal Program Memory is implemented within the PMU.
The instructions requested by the CPU can be located in the Internal Program Memory;
in which case, the instructions are requested to the internal memory. Alternatively, they
can be located in external memory; in which case, the PMU re-sends this request to the
EBC through the DMU, receives the data from the external memory, through the EBC/
DMU, and delivers it as the requested instruction to the CPU.