Infineon Technologies C166S V2, User Manual

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User Manual
C166S V2
Interrupt and Exception Handling
User Manual 5-135 V 1.7, 2001-01
Note: The trap service routine must clear the respective trap flag; otherwise, a new trap
will be requested after exiting the service routine. Setting a trap request flag by
software causes the same effects as if it had been set by hardware.
The reset functions (hardware, software, watchdog) may be also regarded as a type of
trap. Reset functions have the highest priority (trap priority III). Class A traps have the
second highest priority (trap priority II). At the third rank are Class B traps (trap priority I);
thus, a Class A trap can interrupt a Class B trap.
Class A Trap
Class A traps are generated by the high priority system NMI or by special CPU events
such as the software break, a stack overflow, or an underflow event. Class A traps are
PRTFLT
1)
[3] rwh Protection Fault
0 No protection fault event detected
1 Protection fault event detected
ILLOPA
1)
[2] rwh Illegal word operand access
0 No illegal word operand access event
detected
1 Illegal word operand access event detected
1)
This Bit supports bit-protection
2)
Parity fault on instruction fetch interface, usable for memories with parity check.
Table 5-2 Hardware Trap Summary
Exception Condition Trap
Flag Trap
Vector Trap
Number Trap
Priority
Reset Functions:
Hardware Reset
Software Reset
Watchdog Timer Overflow RESET
RESET
RESET 00
H
00
H
00
H
III
III
III
Class A Hardware Traps:
Non-Maskable Interrupt
Stack Overflow
Stack Underflow
Software Break NMI
STKOF
STKUF
SOFTBRK NMITRAP
STOTRAP
STUTRAP
SBRKTRAP 02
H
04
H
06
H
08
H
II.3
II.2
II.1
II.0
Class B Hardware Traps:
Undefined Opcode
Parity Fault
Protection Fault
Illegal Word Operand Access UNDOPC
PARFLT
PRTFLT
ILLOPA BTRAP
BTRAP
BTRAP
BTRAP 0A
H
0A
H
0A
H
0A
H
I
I
I
I
Field Bits Type Description