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User Manual

C166S V2

Detailed Instruction Description

User Manual

8-396

V 1.7, 2001-01

CoMULsu

Mixed Multiply

CoMULsu

Group

Multiply/Multiply-Accumulate Instructions

Syntax

CoMULsu op1, op2

Source Operand(s)

op1, op2

→

WORD

Destination Operand(s)

ACC

→

40-bit signed value

Operation

(ACC)

←

(op1) * (op2)

Description

Multiplies the two signed and unsigned 16-bit source operands op1 and op2,
respectively. The resulting signed 32-bit product is first sign-extended before being
stored in the 40-bit ACC register.

MAC Flags

MV

Always cleared.

MSL

Not affected.

ME

Always cleared.

MSV

Not affected.

MC

Always cleared.

MZ

Set if result equals zero. Cleared otherwise.

MN

Set if the most significant bit of the result is set. Cleared otherwise.

Encoding

MV

MSL

ME

MSV

MC

MZ

MN

Sat.

0

-

0

-

0

*

*

no

Mnemonic

Format

Bytes

CoMULsu

Rw

n

, Rw

m

A3 nm 40 rrr0:0000

4

CoMULsu

Rw

n

, [Rw

m

*]

83 nm 40 rrr0:0qqq

4

CoMULsu

[IDXi*] , [Rw

m

*]

93 Xm 40 rrr0:0qqq

4

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Summary of Contents for C166S V2

Page 1: ...N e v e r s t o p t h i n k i n g Microcontrollers User Manual V 1 7 January 2001 C166S V2 16 Bit Microcontroller...

Page 2: ...st Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide see address list Warnings Due to technical requirements components may contain dangerous substances Fo...

Page 3: ...Microcontrollers User Manual V 1 7 January 2001 N e v e r s t o p t h i n k i n g C166S V2 16 Bit Microcontroller...

Page 4: ...st revision We Listen to Your Comments Any information within this document that you feel is wrong unclear or missing at all Your feedback will help us to continuously improve the quality of this docu...

Page 5: ...Flow 24 2 3 3 1 Correctly Predicted Instruction Flow 24 2 3 3 2 Incorrectly Predicted Instruction Flow 26 2 3 4 Atomic and Extend Instructions 27 2 3 5 Code Addressing via Code Segment and Instruction...

Page 6: ...2 2 7 9 The Repeat Counter MRW 84 2 7 10 The MAC Unit Status Word MSW 85 2 7 11 The MAC Unit Control Word MCW 88 2 8 Dedicated CSFRs 89 3 C166S V2 Memory Organization 91 3 1 Data Organization in Memor...

Page 7: ...ler Interrupt Actions Summary 147 5 4 4 PEC Channel Assignment and Arbitration 149 5 5 CPU Action Control Unit 151 6 External Bus Controller 153 6 1 Introduction 153 6 2 Timing Principles 154 6 2 1 A...

Page 8: ...ary 178 7 3 Instruction Opcodes 192 8 Detailed Instruction Description 205 8 1 Normal Instruction Set 212 8 2 DSP Instruction Set 315 8 3 Instructions for OCDS ITC injection and System Control 417 9 S...

Page 9: ...ory structure and multiple high speed data buses provide transparent data access 0 cycles and broad bandwidth for efficient DSP processing Advanced exceptions handling block with multi stage arbitrati...

Page 10: ...tion High performance branch call and loop processing Multiply and accumulate instructions MAC executed in one CPU clock cycle Extremely short interrupt response time Fast interrupt and Fast context s...

Page 11: ...ion facilities Zero cycle jump execution Additional instructions to support HLL and operating systems Register based design with multiple variable register banks Two additional fast register banks Gen...

Page 12: ...Data Management Unit DMU handles all data transfers external to the core i e external memory or on chip special function registers on the PDBUS and instruction fetches in external memory The DMU acts...

Page 13: ...uring break or monitor mode Simple monitor mode or JTAG based debugging through instruction injection The C166S V2 OCDS is controlled by the debugger1 through a set of registers accessible from the JT...

Page 14: ...erals connected to this bus is programmable according to the maximum physical bus speed and the application requirements Furthermore the clock generation status is indicated Depending on the applicati...

Page 15: ...re address data in data out CSP IP CPUCON1 CPUCON2 FIFO IFU IDX0 IDX1 QX1 QX0 QR1 QR0 SP SPSEG VECSEG STKOV STKUN DPP0 DPP1 DPP3 DPP2 ADU MDL MDH MAL Division Unit MAH Multiply Unit MSW MCW ALU RF ZER...

Page 16: ...essing with instruction flow prediction Return Stack Injection Exception Handler Handling of Interrupt Requests Handling of Hardware Failures Instruction Pipeline IPIP Bypassable 2 stage Prefetch Pipe...

Page 17: ...Name of bit bitfieldX Name of bitfield A16 A8 Long 16 bit address Short 8 bit address SFR b ESFR b Register space SFR or ESFR bit addressable Register XSFR Register located in the internal 4 k IO area...

Page 18: ...SFRs in the CPU core is identical to the access mechanism for any other SFR Since all SFRs can be controlled by any instruction capable of addressing the SFR CSFR memory space there is no need for spe...

Page 19: ...fetch a new instruction at a predicted target address from the PMU The latency time of this access is hidden by the execution of the instructions which have been buffered in the FIFO before Even for...

Page 20: ...ng instruction The target address is also used to pre fetch the next instructions For the Execution Pipeline both instructions are fetched from the FIFO again and are executed in parallel If the instr...

Page 21: ...nch target instruction address is determined indi rectly by the contents of a word GPR In contrast to indirect data addresses indirectly specified code addresses are NOT calculated via additional poin...

Page 22: ...ructions with user programmable branch prediction JMPA xcc caddr JMPA xcc caddr CALLA xcc caddr CALLA xcc caddr The User can specify whether the branch should be taken Branch instructions with branch...

Page 23: ...fetch hint bit is used the instruction bit 9 l This bit is required by the fetch unit to deal efficiently with short backward loops It must be set if 0 IP_jmpa IP_target 32 where IP_jmpa is the addre...

Page 24: ...re executed in one CPU cycle while Instruction In 6 takes two CPU cycles for the execution In 6 is a general example for multicycle instructions two cycles instruction in this case The instructions ar...

Page 25: ...H 96 bit Buffer In 6 In 9 In 9 In 11 In 12 In 13 In 14 In 15 In 15 In 19 In 15 In 19 In 16 In 19 In 17 In 19 In 18 In 21 FETCH Instruction Buffer In 5 In 6 In 7 In 8 In 9 In 10 In 11 In 12 In 13 In 14...

Page 26: ...the target instruction crosses the 64 bit memory boundary and a second fetch in Tn 3 is required to get the entire 32 bit instruction In Tn 4 the Prefetch Buffer contains two 32 bit instructions while...

Page 27: ...ruction The ATOMIC and EXTended instructions can be used with any instruction type Note If a class B trap interrupt occurs during an ATOMIC or EXTended sequence then the sequence is terminated an inte...

Page 28: ...IP results directly in a correct 24 bit physical memory address Figure 2 7 Addressing via the Code Segment and Instruction Pointer The Instruction Pointer IP This register determines the 16 bit intra...

Page 29: ...a operations There are two modes segmented and non segmented The mode is selected with the SGTDIS bit in the CPUCON1 register After reset the segmented mode is selected Note For a summary of the CPUCO...

Page 30: ...lly loaded with the segment address of the vector location VECSEG Note For the correct execution of interrupt tasks the contents of VECSEG must be the same as the segment selected by the current value...

Page 31: ...e between two vectors is 16 words WDTCTL 4 rw Configuration of Watch Dog Timer 0 DISWDT executable until End of Init1 1 DISWDT ENWDT always executable SGTDIS 3 rw Segmentation Disable Enable Control 0...

Page 32: ...ss path from prefetch to decode available BYPF 8 rw Fetch Bypass control 0 Bypass path from fetch to decode disabled 1 Bypass path from fetch to decode available EIOIAEN 7 rw Early IO Injection Acknow...

Page 33: ...jection enabled SL 0 rw Enables short loop mode 0 Short loop mode disabled 1 Short loop mode enabled 1 enables dedicated stall debug instructions STALLAM da ha dm hm Opcode 44 dahadmhm STALLEW de he d...

Page 34: ...internal DPRAM One bank uses a block of 16 consecutive words A Context Pointer CP register determines the base address of the current selected bank Because of the required number of access ports and...

Page 35: ...emory mapped GPR bank of the C166 family which is selected by the context pointer CP To support a very fast context switch for time critical tasks two independent not memory mapped GPR banks are avail...

Page 36: ...r instructions are executed After validation all further accesses to the GPRs are redirected to the global register bank If the global register bank is activated there are three possible ways to acces...

Page 37: ...ng Modes 24 Bit Memory Addresses can be directly used to access GPRs In this case the CPU immediately starts the memory access At the same time a hit detection logic checks if the accessed memory loca...

Page 38: ...Register R2 UUUUH R3 CP 6 F3H 3h General Purpose Word Register R3 UUUUH R4 CP 8 F4H 4h General Purpose Word Register R4 UUUUH R5 CP 10 F5H 5h General Purpose Word Register R5 UUUUH R6 CP 12 F6H 6h Ge...

Page 39: ...h General Purpose Byte Register RL1 UUH RL1 CP 2 F2H 2h General Purpose Byte Register RL2 UUH RH1 CP 3 F3H 3h General Purpose Byte Register RL3 UUH RL2 CP 4 F4H 4h General Purpose Byte Register RL4 UU...

Page 40: ...off within a range from F0H to FFH interpret the four least significant bits as short 4 bit GPR address while the four most significant bits are ignored The respective physical GPR address calculation...

Page 41: ...ank is not valid at this time in case if the context switch process has been interrupted the cache validation process is repeated automatically For further explanation please refer to Section 2 4 3 2...

Page 42: ...register file context switch is really executed The instruction immediately following the instruction that updates CP register can use the new value of the changed CP The C166S V2 CPU switches the com...

Page 43: ...of the global register bank are invalidated 2 Load phase The global register bank is loaded with the new context by executing eight injected LOAD instructions After the last LOAD instruction the conte...

Page 44: ...Task B but the latency of Task C If Task C would immediately interrupt Task A the register bank validation process of Task A would be finished first The worst case interrupt latency is identical in bo...

Page 45: ...aging Standard Address Unit Stack Handling Standard Address Unit The Standard Address Unit supports linear arithmetic for the indirect addressing modes and also generates the address in case of all ot...

Page 46: ...ter bank The reg value requires eight bits in the instruc tion format Short reg addresses in the range from 00H to EFH always specify E SFRs In that case the factor D equates 2 and the base address is...

Page 47: ...ort bitoff addresses in the range from 00H to 7FH use 00 FD00H as a base address to specify the 128 highest internal RAM word locations in the range from 00 FD00Hh to 00 FDFEH Short bitoff addresses i...

Page 48: ...meanings Bits 13 0 specify a 14 bit data page offset while bits 15 14 specify the Data Page Pointer DPP 1 of 4 register used to generate the full 24 bit address see Figure 2 14 The C166S V2 CPU also s...

Page 49: ...accesses via EXTended instructions and PEC data transfers Data paging is performed by concatenating the lower 14 bits of an indirect or direct long 16 bit address with the contents of the DDP register...

Page 50: ...e 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 PN r r r r r r rw DPP1 Data Page Pointer 1 SFR Reset Value 0001H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 PN r r r r r r rw DPP2 Data...

Page 51: ...an override mechanism for the temporary bypass of the DPP addressing scheme The EXTP R and EXTS R instructions override this addressing mechanism Instruction EXTP R replaces the contents of the respec...

Page 52: ...ies the data page offset and the DPP The long addressing mode is referred to by the mnemonic mem Note The long addressing may be used with the DPP overriding mechanism EXTP R and EXTS R Table 2 6 Long...

Page 53: ...ffset Register QR0 and QR1 There are two non bit addressable offset registers QR0 and QR1 which can be used in conjunction with the CoXXX instructions Note During initialization of the QR registers in...

Page 54: ...t address pointer Rw by the data type dependent value D 1 for byte operations D 2 for word operations before the long 16 bit address is generated GPR Address GPR Address D optional step 3 Calculate th...

Page 55: ...ter the access Rw The specified indirect address pointer is automatically pre decremented by 2 or 1 for word or byte data operations before the access Rw data16 The specified 16 bit constant is added...

Page 56: ...cycle Note During the initialization of the IDX registers instruction flow stalls are possible For the proper operation refer to the Section 4 1 4 The address pointers can be used for arithmetic oper...

Page 57: ...igure 2 17 Arithmetic MAC Operations and Addressing via the IDX Pointers For CoMOV MAC operation the IDX pointers are concatenated with the Data Page Pointers just like normal GPR Pointers as describe...

Page 58: ...indirect addressing modes allow decrementing or incrementing the indirect address pointers IDXx contents by 2 or by the contents of the offset registers There are two non bit addressable offset regis...

Page 59: ...DX via the following algorithm 1 Determine the used IDXx pointer 2 An intermediate long address is calculated for the parallel data move opera tion of CoXXXM instructions before the long 16 bit addres...

Page 60: ...D QXx for word operations IDX Pointer IDX Pointer D optional step The following indirect addressing modes are provided Table 2 8 DSP Addressing Modes Mnemonic Particularities IDXx Most CoXXX instruct...

Page 61: ...ter is automatically post incremented by QXx after the access with parallel data move In case of a CoXXXM instruction the address stored in the specified indirect address pointer is automatically pre...

Page 62: ...llel mov operation calculate long 16bit address Long Address 2 R2 4 Physical Address 1 Page3 Page offset calculate 24bit physical address Physical Address 2 DPPi Page offset 5 post modify address poin...

Page 63: ...ation The address of the MAC Unit register is coded in the CoSTORE instruction format as described in the following table Table 2 9 Coding of the CoREG Addressing Mode Mnemonic Register Coding of wwww...

Page 64: ...Pointer SP register is used to point to the top of the system stack TOS The SP register is pre decremented whenever data is to be pushed onto the stack and it is post incremented whenever data is to...

Page 65: ...Figure 2 20 Addressing via the Stack Pointer In case of a non segmented memory mode the SPSG register is also used to generate the physical address If a non segmented memory model is selected extreme...

Page 66: ...tack pointer is compared with the contents of the overflow register whenever the SP is to be decremented either by a CALLA CALLI CALLR CALLS PCALL TRAP SCXT or PUSH instruction Note If the Stack Point...

Page 67: ...the contents of the SP register are equal to the contents of the STKUN register a stack underflow hardware trap will occur The STKUN register can be updated via any instruction capable of modifying a...

Page 68: ...d STKUN detects cases in which the Stack Pointer SP crosses the defined stack area as a result of implicit change Note If a stack overflow or underflow event occurs in an ATOMIC EXT sequence the stack...

Page 69: ...1 128 to 127 BYTE unsigned char 1 0 to 255U BYTE sfr 1 0 to 65535U WORD esfr 1 0 to 65535U WORD signed short 2 32768 to 32767 WORD unsigned short 2 0 to 65535U WORD bitword 2 0 to 65535U WORD or BIT...

Page 70: ...te operations signals from bits 6 and 7 of the ALU result are used to control the condition flags Multiple precision arithmetic is supported by a CARRY IN signal to the ALU from previously calculated...

Page 71: ...the register bank via the Context Pointer CP Even GPRs allocated to not bit addressable RAM locations provide this feature The read modify write approach may be critical with hardware effected bits In...

Page 72: ...ressable MDH register contains the high word of the 32 bit multiply divide MD register used by the CPU when it performs a multiplication or a division using implicit addressing DIV DIVL DIVLU DIVU MUL...

Page 73: ...is read via software The Divide Control Register MDC This bit addressable 16 bit register is implicitly used by the CPU when it performs a division or multiplication in the ALU MDL Multiply Divide Lo...

Page 74: ...separate bits USR0 and USR1 within register PSW are provided as general purpose flags PSW Processor Status Word SFRb Reset Value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ILVL IEN HLD EN BANK USR 1...

Page 75: ...of the result contains a 1 otherwise it is cleared In the case of integer operations the N flag can be interpreted as the sign bit of the result negative N 1 positive N 0 Negative numbers are always...

Page 76: ...Flag The addition subtraction and 2 s complement operations set the V flag to 1 if the result exceeds the range of 16 bit signed numbers for word operations 8000H to 7FFFH or 8 bit signed numbers for...

Page 77: ...n 8000H for the word data type or 80H for the byte data type the E flag is set to 1 otherwise it is cleared MULIP Flag The MULIP flag always sticks to 0 Note The MULIP flag is a part of the C166 task...

Page 78: ...CoXXX arithmetic instructions are performed in the MAC unit The MAC unit provides single instruction cycle non pipelined 32 bit additions 32 bit subtraction right and left shifts 16 bit by 16 bit mul...

Page 79: ...n of Numbers and Rounding The C166S V2 CPU supports the 2s complement representation of binary numbers In this format the sign bit is the MSB of the binary word This is set to zero for positive number...

Page 80: ...CPU cycle The Concatenation Unit concatenates two 16 bit operands to a 32 bit operand before the 32 bit arithmetic operation is executed in the 40 bit adder subtracter The second required operand is...

Page 81: ...32 bit value automatically after every accumulation The round operation is performed by adding 00 00008000H to the result Automatic saturation is enabled by setting the saturation bit the MAC Control...

Page 82: ...of the Adder Subtracter Note Certain precautions are required in case of left shift with saturation enabled Generally if MAE contains significant bits then the 32 bit value in the accumulator is to b...

Page 83: ...s significant bits Most CoXXX operations specify the 40 bit accumulator register as a source and or a destination operand The MAC Unit Accumulator Extension Byte MAE The MAE register is a part of the...

Page 84: ...cuted The register must be pre loaded before it can be used with USRx CoXXX operations MAC operations are able to decrement this counter When an USRx CoXXX instruction is executed the MRW is checked o...

Page 85: ...is executed 20 times Every time the CoMACM instruction is executed the MRW counter is decremented mov MRW 19 loop01 USR1 CoMACM IDX0 R0 ADD R2 2 JMPA cc_nusr1 loop01 Because correctly predicted JMPA i...

Page 86: ...lag values implicitly generated by the MAC unit An explicit read access to the MSW register returns the value of the MSW register after execution of the immediately preceding instruction The MSW regis...

Page 87: ...ion MAE has been generated After a MAC subtraction or a MAC comparison the MC flag indicates a Borrow representing the logical negation of a Carry for the addition This means that the MC flag is set t...

Page 88: ...set The MSL Flag is a Sticky Bit Once set it cannot be affected by the other MAC operations Only a direct write operation can clear the MSL flag MV Flag The addition subtraction and accumulation opera...

Page 89: ...e output of the multiplier is shifted before being added to the accumulator 2 8 Dedicated CSFRs The Constant Zeros Register ZEROS All bits of this bit addressable register are fixed to 0 by hardware T...

Page 90: ...ation Register CPUID This 16 bit register contains the module and revision number of the implemented C166S V2 core module ONES Constant Ones Register SFRb Reset Value FFFFH 15 14 13 12 11 10 9 8 7 6 5...

Page 91: ...of 64 KBytes each Each segment is again subdivided into four data pages of 16 KBytes each see Figure 3 1 Most internal memory areas are mirrored into the system segment segment 0 The upper 4 KBytes of...

Page 92: ...ge 1023 Segment 255 Segment 1 Segment 0 00 0000H 01 0000H 02 0000H FF FFFFH Data Page 3 Data Page 0 FF 0000H External Memory 00 0000H internal IO Area Internal SRAM 00 E000H Segment 64 40 0000H 41 000...

Page 93: ...t of the byte at an even byte address and bit position 15 is the most significant bit of the byte at the next odd byte address Bit addressing is supported for a part of the Special Function Registers...

Page 94: ...ble Note The x in the locations above depend on the available Internal Program Memory 3 3 DPRAM Internal SRAM and SFR Areas The C166S V2 CPU differentiates between various internal memory types and in...

Page 95: ...or long 16 bit addressing modes if the selected DPP register points to data page 3 or data page 2 Any word data access is made on an even byte address The highest possible word data storage location i...

Page 96: ...e SFR and ESFR memory area an internal peripheral bus access is executed using the respective long address instead of a GPR access The upper half of each register block except the 16 highest words ref...

Page 97: ...nables a read instruction to read a memory location before a preceding write instruction has executed its write access Data forwarding guarantees the correct instruction flow execution In case of an I...

Page 98: ...sed via the external bus interface This interface may further limit the amount of addressable external memory External word and byte data can be accessed only via indirect or long 16 bit addressing mo...

Page 99: ...t be switched explicitly The instructions JMPS CALLS and RETS will do this Larger sequential programs make sure that the highest used code location of a segment contains an unconditional branch instru...

Page 100: ...1 Data Organization in Global General Purpose Registers The C166S V2 CPU differentiates between global memory mapped General Purpose Register GPR banks and local not mapped GPR banks In addition to t...

Page 101: ...o sixteen word GPRs R0 R1 R15 and or of up to sixteen byte GPRs RL0 RH0 RL7 RH7 The sixteen byte GPRs are mapped onto the first eight word GPRs see table above In contrast to the system stack a regist...

Page 102: ...User Manual C166S V2 C166S V2 Memory Organization User Manual 3 102 V 1 7 2001 01...

Page 103: ...predicted order The instructions are pre processed in the branch detection unit to detect branches The prediction logic decides if the branches are assumed to be taken or not 2st FETCH The instructio...

Page 104: ...d way without performance loss This makes the pipeline unnoticeable for the user in most cases However there are some rare cases in which the C166S V2 CPU pipeline requires attention by the programmer...

Page 105: ...ue of the GPR is calculated in the execute stage while the instruction using an indirect addressing mode accesses the GPR already in the Decode Stage The instruction is stalled in the address stage un...

Page 106: ...SRAM etc is selected according to a history table before the address is decoded This history table has one entry for each of the Tn Tn 1 Tn 2 Tn 3 Tn 4 Tn 5 DECODE In ADD R0 R1 In 1 MOV R3 R0 In 2 In...

Page 107: ...width Conflicts Memory bandwidth conflicts can occur if instructions in the pipeline access the same memory area at the same time Special access mechanisms are implemented in the C166S V2 CPU to minim...

Page 108: ...an generate a DPRAM bandwidth conflict The DPRAM is a synchronous pipelined memory The read access starts with the valid addresses on the address stage The data are delivered in the Memory stage If a...

Page 109: ...xecuting a filter routine One of the operands should be located in the internal SRAM to guarantee a single cycle execution time of the CoXXX instructions In 1 In ADD op1 R1 In 1 ADD R6 R0 In 2 CoMAC I...

Page 110: ...Meanwhile without conflict detection the instructions in the Decode Address and Memory stages would still work without updated register values The C166S V2 CPU detects conflict cases and stalls the pi...

Page 111: ...1 ADD R6 R0 In 2 ADD R6 R1 In 3 MOV R3 R0 In 4 Tn Tn 1 Tn 2 Tn 3 Tn 4 Tn 5 DECODE In MOV MCW 16 In 1 ADD R6 R0 In 2 ADD R6 R1 In 3 MOV R3 R0 In 4 In 5 ADDRESS In 1 In MOV MCW 16 In 1 ADD R6 R0 In 2 A...

Page 112: ...R0 In 2 MOV R6 MDL In 3 ADD R6 R1 In 4 Tn Tn 1 Tn 2 Tn 3 Tn 4 Tn 5 DECODE In MUL R0 R1 In 1 MOV R6 MDL In 2 ADD R6 R1 In 3 MOV R3 R0 In 3 MOV R3 R0 In 4 ADDRESS In 1 In MUL R0 R1 In 1 MOV R6 MDL In 2...

Page 113: ...lowing list are held in the decode stage All other instructions are not held Instructions using long addressing mode mem Instructions using indirect addressing modes Rw Rw except JMPI and CALLI ENWDT...

Page 114: ...S In 1 In MOV IDX1 12 In 1 MOV R6 mem MEMORY In 2 In 1 In MOV IDX1 12 EXECUTE In 3 In 2 In 1 In MOV IDX1 12 WRITE BACK In 4 In 3 In 2 In 1 In MOV IDX1 12 Tn Tn 1 Tn 2 Tn 3 Tn 4 Tn 5 DECODE In MOV IDX1...

Page 115: ...nstructions on the Address and Decode Stage are stalled If the instruction reaches the execute stage the entire pipeline and the Instruction FIFO of the IFU are canceled The instruction flow is comple...

Page 116: ...User Manual C166S V2 Instruction Pipeline User Manual 4 116 V 1 7 2001 01...

Page 117: ...in response to special conditions that occur during the execution of instructions A trap can also be caused externally by the Non Maskable Interrupt pin NMI Several hardware trap functions are provid...

Page 118: ...des are incorporated for efficient use of system resources These nodes can be activated by various source requests The C166S V2 CPU provides a vectored interrupt system This system reserves specific v...

Page 119: ...ter SRCP0 SRCP1 SRCP7 DSTP0 DSTP1 DSTP7 PECSEG0 PECSEG1 PECSEG7 Interrupt Handler Interrupt Request EOP INT 2 Interrupt Handler Control EOPIC PECISNC Fast Bank Switching BNKSEL0 BNKSEL3 Interrupt Jump...

Page 120: ...e interrupt request flag in the corresponding interrupt control register bit xxIC xxIR The interrupt request can also be triggered by the software if the program sets the respective interrupt request...

Page 121: ...The second arbitration stage compares the priority of the first stage winner with the priority of OCDS service requests C166S V2 OCDS service requests bypass the first stage of arbitration and go dire...

Page 122: ...evel of the CPU Therefore a request on interrupt priority level 0000B will be arbitrated but the CPU will never accept an action request on this level However every enabled interrupt request including...

Page 123: ...rw rw rw Field Bits Type Description GPX 8 rw Group Priority Extension Defines the value of high order group level bit xxIR1 1 Bit xxIR supports bit protection 7 rwh Interrupt Request Flag 0 No reques...

Page 124: ...s These routines may be located anywhere within the address space The location and organization of the vector table is programmable The vector table can be located in all segments with exception of th...

Page 125: ...ially if memories with a high latency are used such as DRAMs Therefore avoiding the vector table may significantly improve interrupt response time However the number of 24 bit vectors in the ITC is li...

Page 126: ...rw rw Field Bits Type Description EN 15 rw Fast Interrupt Enable 0 The interrupt jump table cache is disabled No fast interrupt is used 1 The interrupt jump table cache is enabled A fast interrupt dir...

Page 127: ...ted interrupt jump table cache entry SEG 7 0 rw Segment Number of Interrupt Service Routine This bit field specifies address bits 23 16 of the interrupt service routine s entry point FINT0ADDR Fast In...

Page 128: ...the PSW Hardware traps set the CPU level to the maximum priority 15 Therefore no interrupt or PEC requests will be acknowledged while an exception trap service routine is being executed The TRAP inst...

Page 129: ...sk status The C166S V2 CPU saves the CPU status PSW along with the return address in the system stack The return address defines the point at which the execution of the interrupted task is to be resum...

Page 130: ...saving and restoring The C166S V2 CPU allows the complete bank of CPU registers GPRs to be switched so the service routine executes within its own separate context There are two ways to switch a conte...

Page 131: ...ns during context switching that are associated with pipeline behavior For details see Section 2 4 3 2 5 2 4 Fast Bank Switching The interrupt handler of the C166S V2 CPU supports an additional enhanc...

Page 132: ...or location of the vector table will be used Table 5 1 Register Bank Assignment Interrupt Priority Level ILVL Group Priority Level XGLVL Assigned GPRSELx Register Interrupt Priority Level ILVL Group P...

Page 133: ...ware Traps Hardware Traps are issued by faults or specific system states that occur during runtime not identified at compile time The C166S V2 CPU distinguishes eight different hardware trap functions...

Page 134: ...4 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NMI STK OF STK UF SOFT BRK 0 0 0 0 UND OPC 0 0 PAR FLT PRT FLT ILL OPA 0 0 rwh rwh rwh rwh r r r r rwh r r rwh rwh rwh r r Field Bits Type Description NMI1 15 rwh Non...

Page 135: ...erflow event Class A traps are PRTFLT1 3 rwh Protection Fault 0 No protection fault event detected 1 Protection fault event detected ILLOPA1 2 rwh Illegal word operand access 0 No illegal word operand...

Page 136: ...n execution of branch instructions in parallel with the preceding instruction The pre processed branch instruction is combined with the preceding instruction The branch is executed together with the i...

Page 137: ...truction following the one which caused the trap is pushed into the stack and the Class A trap is executed If this occurs during execution of an atomic extend sequence or I O read access in progress t...

Page 138: ...ess the ILLOPA flag in register TFR is set and the CPU enters the illegal word operand access trap routine 5 4 Peripheral Event Controller The Peripheral Event Controller PEC makes a decision about th...

Page 139: ...d of PEC Interrupt Selection 0 End of PEC interrupt with the same level as the PEC transfer is trigger 1 End of PEC interrupt is serviced by a separate interrupt node with programmable interrupt level...

Page 140: ...C transfer and the request flag is cleared to indicate that the request has been serviced When COUNT reaches 00H it immediately activates the interrupt service routine that has the same priority level...

Page 141: ...request pending 1 The source has raised an interrupt request EOPIE 6 rw Interrupt Enable Control Bit 0 Interrupt request is disabled 1 Interrupt request is enabled ILVL 5 2 rw Interrupt Priority Leve...

Page 142: ...quest of PEC channel x is disabled 1 End of PEC interrupt request of PEC channel x is enabled 1 x 7 0 2 NOTE The End of PEC sub node interrupt request flags are not cleared by hardware when entering t...

Page 143: ...f PEC Interrupt Sub Node Table 5 3 summarizes the values the bit field COUNT and the corresponding PEC channel actions PECISNC 0 C0IE 15 C0IR C1IE C1IR C5IE C5IR C3IR C4IE C4IR C2IE C2IR C3IE C6IE C6I...

Page 144: ...Channel Actions Previous COUNT Field Value Modified COUNT Field Value Action of PEC Channel and Comments FFH FFH Move a Byte Word Continuous transfer mode COUNT is not modified FEH 02H FDH 01H Move a...

Page 145: ...interrupt but no PEC transfer So the channel pair is assigned to the interrupt and group level of the even numbered channel partner After the first initialization for linked transfer the transfer is s...

Page 146: ...sfers BWT 1 or FFFEH in the case of word transfers BWT 0 the next increment will be disregarded The address register will keep one of these maximum values and no overflow will happen The described beh...

Page 147: ...the bitfield COUNT SRCPx PEC Source Pointer x 7 0 XSFR Reset Value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SRCPx rwh Field Bits Type Description SRCPx 15 0 rwh Source Pointer Address of Channel x...

Page 148: ...winner is cleared and will not trigger more actions Interrupt request flag of the end of PEC interrupt subnode will be set PECISNC CxIR 1 If the respective interrupt enable flag of the end of PEC inte...

Page 149: ...0 to 3 can be associated with the PEC functionality eight PEC channels in total The group extension is not supported for PEC requests because the 8 PEC channels are assigned to two interrupt levels fo...

Page 150: ...l PEC Channel x Arbitration Priority Level PEC Channel x Interrupt Priority Level xxIC ILVL Group Priority Level xxIC XGLVL PLEV Ch Interrupt Priority Level xxIC ILVL Group Priority Level xxIC XGLVL P...

Page 151: ...nding requester The OCDS requests have programmable priority levels If another interrupt request that has won an arbitration conflicts with an OCDS request the one with the higher priority will trigge...

Page 152: ...User Manual C166S V2 Interrupt and Exception Handling User Manual 5 152 V 1 7 2001 01...

Page 153: ...a specific address area which is defined via the corresponding address select register ADDRSELx The seven register sets FCONCS1 TCONCS1 ADDRSEL1 to FCONCS7 TCONCS7 ADDRSEL7 define seven independent ad...

Page 154: ...e low active WRH Write High Byte Strobe low active configured either to an enable for the high byte or a write request for the high byte see Table 6 1 RD Read Strobe low active READY Ready to indicate...

Page 155: ...addresses valid ALE low no command R W delay d phase write data valid ALE low no command Data valid for write cycles e phase command read or write active Access time f phase command inactive address h...

Page 156: ...Address hold R W delay d phase address tristate for read cycles data valid for write cycles ALE low no command e phase command read or write active Access time f phase command inactive address hold R...

Page 157: ...nd two idle cycles occurred then the A Phase takes only one clock cycle 6 2 2 B Phase The B phase can take 1 2 clocks It is used for selecting devices and registers before giving a command and to defi...

Page 158: ...e of the chipselect windows Startup and Monitor Memory registers to control the access to these dedicated memories CS0 is the default chip select that selects all address space not addressed by anothe...

Page 159: ...Disable 0 ALE enabled 1 ALE disabled1 BYTDIS 12 rw BHE pin Disable 0 BHE enabled 1 BHE disabled1 WRCFG2 11 rw Configuration for pins WR WRL BHE WRH 0 WR and BHE 1 WRL and WRH EBCDIS 10 rw EBC pins Di...

Page 160: ...he next external bus access cycle EBC Mode Register 1 EBCMOD1 XSFR Reset value 0000H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 DHP DIS 0 APDIS r r r r r r r r r rw r rw Bits Typ Descript...

Page 161: ...and not changeable for the built in memories Timing Configuration Register for Chip Select Channel 0 TCONCS0 XSFR Reset value 6243H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 WRPHF RDPHF PHE PHD PHC PHB...

Page 162: ...ase of a write access WRPHF 14 13 rw Write Phase F 00 0 clock cycles 11 3 clock cycles RDPHF 12 11 rw Read Phase F 00 0 clock cycles 11 3 clock cycles PHE 10 6 rw Phase E 00000 1 clock cycle 11111 32...

Page 163: ...11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 BTYP 0 RDY MOD RDY EN EN CS r r r r r r r r r r rw r rw rw rw Function Configuration Register for Chip Select Channel x FCONCSx XSFR Reset value 0000H 15...

Page 164: ...YMOD 2 rw Ready Mode 0 asynchronous READY 1 synchronous READY RDYEN 1 rw Ready enable 0 access time is controlled by bitfield PHEx 1 access time is controlled by bitfield PHEx and READY signal ENCS1 0...

Page 165: ...e for startup and monitor memory and the area from C0 0000H to FF FFFFH 4 Mbyte is used by the internal program memory Therefore these address areas cannot be used by external resources connected to t...

Page 166: ...ers ADDRSELy An overlapping of windows of this group will lead to an undefined behaviour Priority 3 A match with registers ADDRSELy y 1 3 5 7 directs the access to the respective external area using t...

Page 167: ...ives READY active in order to indicate that data has been latched write cycle or is available read cycle The READY pin is generally enabled by setting the bit RDYDIS in EBCMOD0 to 0 in order to switch...

Page 168: ...e or READY control logic takes a while to generate the READY signal when a cycle was started After a predefined number of clock cycles the C166S V2 will start checking its READY line to determine the...

Page 169: ...tristate except pin BREQ which is pulled inactive After reset the C166S V2 EBC always starts in init mode where the external bus is available but no arbitration is enabled All arbitration pins are ign...

Page 170: ...el until the arbitration slave frees the bus by releasing its request on the HOLD input If the arbitration master is not the owner of the bus it treats the external bus interface as follows Address an...

Page 171: ...s configured as arbitration slave it is by default not owner of the external bus and has to request the bus first As long as it has not finished all its queued requests and the arbitration master is n...

Page 172: ...er and the other as arbitration slave can be connected directly together as shown in Figure 6 10 As both EBCs assume after reset to own the external bus the slave CPU has to be released from reset and...

Page 173: ...ible external access The following four figures show the principal possible fastest access type for the EBC Figure 6 11 Fastest Read Cycle Demultiplexed Bus Figure 6 12 Fastest Write Cycle Demultiplex...

Page 174: ...74 V 1 7 2001 01 Figure 6 13 Fastest Read Cycle Multiplexed Bus Figure 6 14 Fastest Write Cycle Multiplexed Bus ALE ADDR CS RD valid muxed Address out DATA in d valid b f CLK add valid e ALE ADDR CS W...

Page 175: ...ons by their mnemonic and identifies the addressing modes that may be used with the specific instructions and indicates the instruction length for the selected addressing mode This reference helps to...

Page 176: ...SUB SUBC XOR AND OR x5 ADDB ADDCB SUBB SUBCB XORB ANDB ORB x6 ADD ADDC SUB SUBC CMP XOR AND OR x7 ADDB ADDCB SUBB SUBCB CMPB XORB ANDB ORB x8 ADD ADDC SUB SUBC CMP XOR AND OR x9 ADDB ADDCB SUBB SUBCB...

Page 177: ...V MOV MOVB MOVB MOV MOV MOVB MOVB x5 ENWDT DIS WDT EINIT MOVBZ MOVBS x6 CMPI1 CMPI2 CMPD1 CMPD2 SCXT SCXT MOV MOV x7 IDLE PWRDN SRV WDT SRST EXTP S R MOVB MOVB x8 MOV MOV MOV MOV MOV MOV MOV x9 MOVB M...

Page 178: ...ress Offset Register QR QR0 QR1 reg SFR or GPR in case of a byte operation on an SFR only the low byte can be accessed via reg mem Direct word or byte memory location Indirect word or byte memory loca...

Page 179: ...dress Updates the Instruction Pointer seg Direct 2 bit segment address Updates the Code Segment Pointer rel Signed 8 bit jump target word offset address relative to the Instruction Pointer of the foll...

Page 180: ...V Overflow cc_NV No Overflow cc_N Negative cc_NN Not Negative cc_C Carry cc_NC No Carry cc_EQ Equal cc_NE Not Equal cc_ULT Unsigned Less Than cc_ULE Unsigned Less Than or Equal cc_UGE Unsigned Greater...

Page 181: ...bitaddrZ z bitaddrQ q 4 CMP B Rwn Rwm 1 Rwn Rwi 1 Rwn Rwi 1 Rwn data3 1 reg data16 2 reg mem 2 2 2 2 4 4 BCLR BSET bitaddrQ q 2 CALLA JMPA cc caddr 4 BFLDH BFLDL bitoffQ mask8 data8 4 CALLI JMPI cc Rw...

Page 182: ...ister 4 ADDB reg mem Add direct byte memory to direct register 4 ADDB mem reg Add direct byte register to direct memory 4 ADDC Rw Rw Add direct word GPR to direct GPR with Carry 2 ADDC Rw Rw Add indir...

Page 183: ...direct register 4 SUBB reg mem Subtract direct byte memory from direct register 4 SUBB mem reg Subtract direct byte register from direct memory 4 SUBC Rw Rw Subtract direct word GPR from direct GPR w...

Page 184: ...AND direct word GPR with direct GPR 2 AND Rw Rw Bitwise AND indirect word memory with direct GPR 2 AND Rw Rw Bitwise AND indirect word memory with direct GPR and post increment source pointer by 2 2...

Page 185: ...irect byte memory with direct register 4 ORB mem reg Bitwise OR direct byte register with direct memory 4 XOR Rw Rw Bitwise XOR direct word GPR with direct GPR 2 XOR Rw Rw Bitwise XOR indirect word me...

Page 186: ...2 CMP Rw Rw Compare indirect word memory to direct GPR 2 CMP Rw Rw Compare indirect word memory to direct GPR and post increment source pointer by 2 2 CMP Rw data3 Compare immediate word data to dire...

Page 187: ...Rw mem Compare direct word memory to direct GPR and increment GPR by 1 4 CMPI2 Rw data4 Compare immediate word data to direct GPR and increment GPR by 2 2 CMPI2 Rw data16 Compare immediate word data...

Page 188: ...ied by immediate data 2 Data Movement MOV Rw Rw Move direct word GPR to direct GPR 2 MOV Rw data4 Move immediate word data to direct GPR 2 MOV reg data16 Move immediate word data to direct register 4...

Page 189: ...ct memory 2 MOVB Rw Rw Move indirect byte memory to indirect memory 2 MOVB Rw Rw Move indirect byte memory to indirect memory and post increment destination pointer by 1 2 MOVB Rw Rw Move indirect byt...

Page 190: ...l Jump relative if direct bit is not set 4 JNBS bitaddr rel Jump relative and set bit if direct bit is not set 4 CALLA cc caddr Call absolute subroutine if condition is met 4 CALLI cc Rw Call indirect...

Page 191: ...imer 4 ENWDT Enable Watchdog Timer 4 EINIT Signify End of Initialization on RSTOUT pin 4 ATOMIC irang2 Begin ATOMIC sequence 2 EXTR irang2 Begin EXTended Register sequence 2 EXTP Rw irang2 Begin EXTen...

Page 192: ...wo mnemonic representation alternatives exist for some of the condition codes Notes on the JMPA and CALLA Instructions For JMPA and CALLA instructions a static user programmable prediction scheme is u...

Page 193: ...tended control fields in the operand field to specify the special indirect addressing mode Bitfield X is 4 bits wide and is located within CoXXX instructions at bit positions 15 12 Bit 15 specifies on...

Page 194: ...t register addressing uses GPR 2 cycles else bit 1 cycle if at least one bit address is a GPR 2 cycles else co 1 to 2 cycle see table for MAC instructions 0 1 0 cycles if branch is executed zerocycle...

Page 195: ...Rw Rw 2C 2 1 ROR Rw Rw 0D 2 0 1 JMPR cc_UC rel 2D 2 0 1 JMPR cc_EQ rel or cc_Z rel 0E 2 1 BCLR bitoff 0 2E 2 1 BCLR bitoff 2 0F 2 1 BSET bitoff 0 2F 2 1 BSET bitoff 2 10 2 1 ADDC Rw Rw 30 2 1 SUBC Rw...

Page 196: ...HL Rw Rw 6C 2 1 SHR Rw Rw 4D 2 0 1 JMPR cc_V rel 6D 2 0 1 JMPR cc_N rel 4E 2 1 BCLR bitoff 4 6E 2 1 BCLR bitoff 6 4F 2 1 BSET bitoff 4 6F 2 1 BSET bitoff 6 50 2 1 XOR Rw Rw 70 2 1 OR Rw Rw 51 2 1 XORB...

Page 197: ...2 1 ASHR Rw Rw 8D 2 0 1 JMPR cc_C rel or cc_ULT rel AD 2 0 1 JMPR cc_SGT rel 8E 2 1 BCLR bitoff 8 AE 2 1 BCLR bitoff 10 8F 2 1 BSET bitoff 8 AF 2 1 BSET bitoff 10 90 2 1 CMPI2 Rw data4 B0 2 1 CMPD2 Rw...

Page 198: ...1 PUSH reg CD 2 0 1 JMPR cc_SLT rel ED 2 0 1 JMPR cc_UGT rel CE 2 1 BCLR bitoff 12 EE 2 1 BCLR bitoff 14 CF 2 1 BSET bitoff 12 EF 2 1 BSET bitoff 14 D0 2 1 MOVBS Rw Rb F0 2 1 MOV Rw Rw D1 2 1 ATOMIC o...

Page 199: ...MULsu RWn RWm rnd 83 42 1 CoADD2 RWn RWm 83 48 1 CoMULsu RWn RWm 83 4A 1 CoSUB2 RWn RWm 83 50 1 CoMACsu RWn RWm 83 51 2 CoMACsu RWn RWm rnd 83 52 1 CoSUB2R RWn RWm 83 60 1 CoMACsu RWn RWm 83 62 1 CoLO...

Page 200: ...u IDXi RWm 93 2A 1 CoLOAD IDXi RWm 93 30 1 CoMACRu IDXi RWm 93 31 2 CoMACRu IDXi RWm rnd 93 38 1 CoMACMRu IDXi RWm 93 39 2 CoMACMRu IDXi RWm rnd 93 3A 1 CoMAX IDXi RWm 93 40 1 CoMULsu IDXi RWm 93 41 2...

Page 201: ...m rnd 93 C2 1 CoCMP IDXi RWm 93 C8 1 CoMUL IDXi RWm 93 CA 1 CoABS IDXi RWm 93 D0 1 CoMAC IDXi RWm 93 D1 2 CoMAC IDXi RWm rnd 93 D8 1 CoMACM IDXi RWm 93 D9 2 CoMACM IDXi RWm rnd 93 E0 1 CoMAC IDXi RWm...

Page 202: ...n RWm A3 80 1 CoMULus RWn RWm A3 81 2 CoMULus RWn RWm rnd A3 82 1 CoSHL data5 A3 88 1 CoMULus RWn RWm A3 8A 1 CoSHL RWn A3 90 1 CoMACus RWn RWm A3 91 2 CoMACus RWn RWm rnd A3 92 1 CoSHR data5 A3 9A 1...

Page 203: ...ual C166S V2 Instruction Set User Manual 7 203 V 1 7 2001 01 A3 F1 2 CoMACR RWn RWm rnd B3 1 CoSTORE RWn CoReg C3 1 CoSTORE RWn CoReg D3 00 2 CoMOV IDXi RWm Hex code Extended Hex code Cycles Mnemonic...

Page 204: ...User Manual C166S V2 Instruction Set User Manual 7 204 V 1 7 2001 01...

Page 205: ...ng mode All of the available addressing modes are summarized at the end of each single instruction description In contrast to the syntax for the instructions described in the following material the as...

Page 206: ...ide register 32 bits wide consists of MDH and MDL MDL MDH Multiply Divide Low and High registers each 16 bit wide ACC Accumulator 40 bits wide consists of MAE MAH and MDL MAH MAL Accumulator Low and H...

Page 207: ...by the respective instruction Condition Code The Condition code indicates that the respective instruction is executed if the specified condition exists and is skipped if it does not The table below s...

Page 208: ...tic Overflow occurred during operation V 0 No Arithmetic Overflow occurred during operation Z 1 Result equals zero Z 0 Result does not equal zero E 1 Source operand represents the lowest negative numb...

Page 209: ...rwritten For bit or bit field operations on the PSW register only the specified bits are modified Supposed that the condition flags were not selected as destination bits they stay unchanged This means...

Page 210: ...pecifier for CoXXX instructions z 4 bit position of the destination bit within the word specified by ZZ 4 bit immediate constant data4 t ttt0 7 bit trap number trap7 QQ 8 bit word address of the sourc...

Page 211: ...rd instructions Figure 8 1 Instruction Format Representation The following pages contain a detailed description of each normal arithmetic logic branch or system instruction in alphabetical order follo...

Page 212: ...the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmetic overflow occurr...

Page 213: ...represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmetic overflow occurred i e the result...

Page 214: ...thmetic CPU Flags E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero and previous Z flag was set C...

Page 215: ...etic CPU Flags E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero and previous Z flag was set Clea...

Page 216: ...ecified by op1 The result is then stored in op1 CPU Flags E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result e...

Page 217: ...fied by op1 The result is then stored in op1 CPU Flags E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equa...

Page 218: ...f the result are filled with zeros if the original most significant bit was a 0 or with ones if the original most significant bit was a 1 The Overflow flag is used as a Rounding flag The least signifi...

Page 219: ...User Manual C166S V2 Detailed Instruction Description User Manual 8 219 V 1 7 2001 01 Encoding Mnemonic Format Bytes ASHR Rwn data4 BC n 2 ASHR Rwn Rwm AC nm 2...

Page 220: ...class A hardware traps to be disabled for a specified number of instructions The ATOMIC instruction becomes immediately active No NOPs are required for normal ATOMIC execution Depending on the value...

Page 221: ...rms a single bit logical AND of the source bit specified by op2 and the destination bit specified by op1 The result is then stored in op1 CPU Flags E Always cleared Z Contains the logical NOR of the t...

Page 222: ...and s op1 BIT Operation op1 0 Description Clears the bit specified by op1 This instruction is primarily used for peripheral and system control CPU Flags E Always cleared Z Contains the logical negatio...

Page 223: ...comparison of the source bit specified by op1 and the source bit specified by op2 No result is written by this instruction Only the flags are updated CPU Flags E Always cleared Z Contains the logical...

Page 224: ...op1 count 8 op3 count ENDIF count count 1 END WHILE Description Replaces those bits in the high byte of the destination word operand op1 which are selected by an 1 in the mask specified by op2 with t...

Page 225: ...1 op1 count op3 count ENDIF count count 1 END WHILE Description Replaces those bits in the low byte of the destination word operand op1 which are selected by an 1 in the mask specified by op2 with the...

Page 226: ...ion op1 op2 Description Moves a single bit from the source operand specified by op2 into the destination operand specified by op1 The source bit is examined and the flags are updated accordingly CPU F...

Page 227: ...n op1 op2 Description Moves the complement of a single bit from the source operand specified by op2 into the destination operand specified by op1 The source bit is examined and the flags are updated a...

Page 228: ...ms a single bit logical OR of the source bit specified by op2 and the destination bit specified by op1 The result is then stored in op1 CPU Flags E Always cleared Z Contains the logical NOR of the two...

Page 229: ...ce Operand s none Destination Operand s op1 BIT Operation op1 1 Description Sets the bit specified by op1 CPU Flags E Always cleared Z Contains the logical negation of the previous state of the specif...

Page 230: ...single bit logical EXCLUSIVE OR of the source bit specified by op2 and the destination bit specified by op1 The result is then stored in op1 CPU Flags E Always cleared Z Contains the logical NOR of t...

Page 231: ...d op2 is taken The value of the instruction pointer IP is placed into the system stack Because the IP always points to the instruction following the branch instruction the value stored in the system s...

Page 232: ...User Manual C166S V2 Detailed Instruction Description User Manual 8 232 V 1 7 2001 01 N Not affected Encoding Mnemonic Format Bytes CALLA xcc caddr CA d00a MM MM 4...

Page 233: ...1 is met a branch to the location specified indirectly by the second operand op2 is taken The value of the instruction pointer IP is placed onto the system stack Because the IP always points to the in...

Page 234: ...lacement is a two s complement number which is sign extended and counts the relative distance in words The value of the instruction pointer IP is placed into the system stack Because the IP always poi...

Page 235: ...absolute location specified by op2 within the segment specified by op1 The previous value of the CSP is placed into the system stack to ensure correct return to the calling segment The value of the in...

Page 236: ...s of subtraction The operands remain unchanged CPU Flags E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result eq...

Page 237: ...f subtraction The operands remain unchanged CPU Flags E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equal...

Page 238: ...s Once the subtraction has completed the operand op1 is decremented by one Using the set flags a branch instruction can then be used in conjunction with this instruction to form common high level lang...

Page 239: ...s Once the subtraction has completed the operand op1 is decremented by two Using the set flags a branch instruction can then be used in conjunction with this instruction to form common high level lang...

Page 240: ...s Once the subtraction has completed the operand op1 is incremented by one Using the set flags a branch instruction can then be used in conjunction with this instruction to form common high level lang...

Page 241: ...s Once the subtraction has completed the operand op1 is incremented by two Using the set flags a branch instruction can then be used in conjunction with this instruction to form common high level lang...

Page 242: ...n Performs a 1s complement of the source operand specified by op1 The result is stored back into op1 CPU Flags E Set if the value of op1 represents the lowest possible negative number Cleared otherwis...

Page 243: ...on Performs a 1s complement of the source operand specified by op1 The result is stored back into op1 CPU Flags E Set if the value of op1 represents the lowest possible negative number Cleared otherwi...

Page 244: ...tion can be executed at any time between the Reset and the first execution of either EINIT or SRVWDT After execution of either an EINIT or a SRVWDT the DISWDT instruction will have no effect If the WD...

Page 245: ...d in the low order word of the MD register MDL and the remainder is stored in the high order word of the MD register MDH CPU Flags E Always cleared Z Set if quotient stored in the MDL register equals...

Page 246: ...tient is then stored in the low order word of the MD register MDL and the remainder is stored in the high order word of the MD register MDH CPU Flags E Always cleared Z Set if quotient stored in the M...

Page 247: ...quotient is then stored in the low order word of the MD register MDL and the remainder is stored in the high order word of the MD register MDH CPU Flags E Always cleared Z Set if quotient stored in t...

Page 248: ...register by the source word operand op1 The unsigned quotient is then stored in the low order word of the MD register MDL and the remainder is stored in the high order word of the MD register MDH CPU...

Page 249: ...time it goes high This enables the software to signal the external circuitry that it has successfully initialized the microcontroller After EINIT execution registers can be locked until reset The DIS...

Page 250: ...register is cleared this instruction has no effect If the WDTCTL bit is set this instruction enables the Watchdog Timer Specifically it allows the Watchdog Timer to be re enabled after it has been pre...

Page 251: ...ssing scheme of the long and indirect addressing modes for a specified number of instructions During their execution both standard and PEC interrupts and class A hardware traps are locked The EXTP ins...

Page 252: ...User Manual C166S V2 Detailed Instruction Description User Manual 8 252 V 1 7 2001 01 Encoding Mnemonic Format Bytes EXTP pag irang2 D7 01 0 pp 0 00pp 4 EXTP Rwm irang2 DC 01 m 2...

Page 253: ...des the standard DPP addressing scheme of the long and indirect addressing modes and causes all SFR or SFR bit accesses via the reg bitoff or bitaddr addressing modes being made to the Extended SFR sp...

Page 254: ...Manual C166S V2 Detailed Instruction Description User Manual 8 254 V 1 7 2001 01 C Not affected N Not affected Encoding Mnemonic Format Bytes EXTPR pag irang2 D7 11 0 pp 0 00pp 4 EXTPR Rwm irang2 DC 1...

Page 255: ...UE Next Instruction count count 1 END WHILE count 0 SFR_range Standard Enable interrupts and traps Description Causes all SFR or SFR bit accesses via the reg bitoff or bitaddr addressing modes being m...

Page 256: ...dard DPP addressing scheme of the long and indirect addressing modes for a specified number of instructions During their execution both standard and PEC interrupts and class A hardware traps are locke...

Page 257: ...User Manual C166S V2 Detailed Instruction Description User Manual 8 257 V 1 7 2001 01 Encoding Mnemonic Format Bytes EXTS seg irang2 D7 00 0 ss 00 4 EXTS Rwm irang2 DC 00 m 2...

Page 258: ...essing scheme of the long and indirect addressing modes and causes all SFR or SFR bit accesses via the reg bitoff or bitaddr addressing modes being made to the Extended SFR space for a specified numbe...

Page 259: ...C166S V2 Detailed Instruction Description User Manual 8 259 V 1 7 2001 01 V Not affected C Not affected N Not affected Encoding Mnemonic Format Bytes EXTSR seg irang2 D7 10 0 ss 00 4 EXTSR Rwm irang2...

Page 260: ...ruction causes the part to enter the idle mode In this mode the CPU is powered down while the peripherals remain running It remains powered down until a peripheral interrupt or external interrupt occu...

Page 261: ...s at the location of the instruction pointer IP plus the specified displacement op2 The displacement is a 2s complement number which is sign extended and counts the relative distance in words The valu...

Page 262: ...perations The displacement is a 2s complement number which is sign extended and counts the relative distance in words The value of the IP used in the target address calculation is the address of the i...

Page 263: ...User Manual C166S V2 Detailed Instruction Description User Manual 8 263 V 1 7 2001 01 Encoding Mnemonic Format Bytes JBC bitaddrQ q rel AA QQ rr q0 4...

Page 264: ...ediction scheme is used if the prediction bit a of the instruction long word is cleared then JMPA is assumed taken and if this bit is set to 1 JMPA is assumed not taken JMPA and JMPA instructions are...

Page 265: ...User Manual C166S V2 Detailed Instruction Description User Manual 8 265 V 1 7 2001 01 C Not affected N Not affected Encoding Mnemonic Format Bytes JMPA xcc caddr EA d0la MM MM 4...

Page 266: ...peration IF op1 1 THEN IP op2 ELSE Next Instruction END IF Description If the condition specified by op1 is met a branch to the absolute address specified by op2 is taken If the condition is not met n...

Page 267: ...execution continues at the location of the instruction pointer IP plus the specified displacement op2 The displacement is a 2s complement number which is sign extended and counts the relative distance...

Page 268: ...gment number op2 16 bit address offset Destination Operand s none Operation IF CPUCON1 SGTDIS 0 THEN CSP op1 END IF IP op2 Description Branches unconditionally to the absolute address specified by op2...

Page 269: ...inues at the location of the instruction pointer IP plus the specified displacement op2 The displacement is a 2s complement number which is sign extended and counts the relative distance in words The...

Page 270: ...operations The displacement is a 2s complement number which is sign extended and counts the relative distance in words The value of the IP used in the target address calculation is the address of the...

Page 271: ...User Manual C166S V2 Detailed Instruction Description User Manual 8 271 V 1 7 2001 01 Encoding Mnemonic Format Bytes JNBS bitaddrQ q rel BA QQ rr q0 4...

Page 272: ...ved data are examined and the flags are updated accordingly CPU Flags E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set...

Page 273: ...ription User Manual 8 273 V 1 7 2001 01 MOV Rwm Rwn B8 nm 2 MOV Rwn Rwm D8 nm 2 MOV Rwn Rwm E8 nm 2 MOV Rwn Rwm C8 nm 2 MOV Rwn mem 84 0n MM MM 4 MOV mem Rwn 94 0n MM MM 4 MOV mem reg F6 RR MM MM 4 MO...

Page 274: ...d data are examined and the flags are updated accordingly CPU Flags E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set i...

Page 275: ...n User Manual 8 275 V 1 7 2001 01 MOVB Rwm Rbn B9 nm 2 MOVB Rwn Rwm D9 nm 2 MOVB Rwn Rwm E9 nm 2 MOVB Rwn Rwm C9 nm 2 MOVB Rwn mem A4 0n MM MM 4 MOVB mem Rwn B4 0n MM MM 4 MOVB mem reg F7 RR MM MM 4 M...

Page 276: ...xtends the contents of the source byte operand specified by op2 to the word location specified by the destination operand op1 The contents of the moved data are examined and the flags are updated acco...

Page 277: ...and zero extends the contents of the source byte operand specified by op2 to the word location specified by the destination operand op1 The contents of the moved data are examined and the flags are up...

Page 278: ...bit by 16 bit signed multiplication using the two words specified by operands op1 and op2 respectively The signed 32 bit result is placed in the MD register CPU Flags E Always cleared Z Set if result...

Page 279: ...bit by 16 bit unsigned multiplication using the two words specified by operands op1 and op2 respectively The unsigned 32 bit result is placed in the MD register CPU Flags E Always cleared Z Set if re...

Page 280: ...y op1 The result is then stored in op1 CPU Flags E Set if the value of op1 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zer...

Page 281: ...by op1 The result is then stored in op1 CPU Flags E Set if the value of op1 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals ze...

Page 282: ...Source Operand s none Destination Operand s none Operation No Operation Description This instruction causes a null operation to be performed A null operation causes no change in the status of the flag...

Page 283: ...pecified by op1 The result is then stored in op1 CPU Flags E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result...

Page 284: ...ified by op1 The result is then stored in op1 CPU Flags E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equ...

Page 285: ...he system stack and branches to the absolute memory location specified by the second operand op2 Because IP always points to the instruction following the branch instruction the value stored on the sy...

Page 286: ...User Manual C166S V2 Detailed Instruction Description User Manual 8 286 V 1 7 2001 01 Encoding Mnemonic Format Bytes PCALL reg caddr E2 RR MM MM 4...

Page 287: ...stack specified by the Stack Pointer into the operand specified by op1 The Stack Pointer is then incremented by two CPU Flags E Set if the value of the popped word represents the lowest possible negat...

Page 288: ...stores a count value in the word operand specified by op1 This count value indicates the number of single bit shifts required to normalize the word operand op2 so that its most significant bit is equa...

Page 289: ...location in the system stack specified by the Stack Pointer after the Stack Pointer has been decremented by two CPU Flags E Set if the value of the pushed operand op1 represents the lowest possible n...

Page 290: ...s mode all peripherals and the CPU are powered down until the device is externally reset To ensure that this instruction is not accidentally executed it is implemented as a protected instruction To fu...

Page 291: ...p Return Instructions Syntax RET Source Operand s none Destination Operand s none Operation IP SP SP SP 2 Description Returns from a subroutine The IP is popped from the system stack CPU Flags E Not a...

Page 292: ...SP SP SP 2 Description Returns from an interrupt routine The IP CSP and PSW are popped off the system stack The CSP is only popped if segmentation is enabled This is indicated by the SGTDIS bit in the...

Page 293: ...irst the IP is popped from the system stack and then the next word is popped from the system stack into the operand specified by op1 CPU Flags E Set if the value of the popped word represents the lowe...

Page 294: ...RETS Source Operand s none Destination Operand s none Operation IP SP SP SP 2 IF CPUCON1 SGTDIS 0 THEN CSP SP END IF SP SP 2 Description Returns from an inter segment subroutine The IP and CSP are po...

Page 295: ...estination word operand op1 the number of times as specified by the source operand op2 Bit 15 is rotated into Bit 0 and into the Carry Only shift values between 0 and 15 are allowed When using a GPR a...

Page 296: ...User Manual C166S V2 Detailed Instruction Description User Manual 8 296 V 1 7 2001 01 Encoding Mnemonic Format Bytes ROL Rwn data4 1C n 2 ROL Rwn Rwm 0C nm 2...

Page 297: ...times as specified by the source operand op2 Bit 0 is rotated into Bit 15 and into the Carry Only shift values between 0 and 15 are allowed When using a GPR as the count control only the least signif...

Page 298: ...User Manual C166S V2 Detailed Instruction Description User Manual 8 298 V 1 7 2001 01 Encoding Mnemonic Format Bytes ROR Rwn data4 3C n 2 ROR Rwn Rwm 2C nm 2...

Page 299: ...re Break Description If the SBRK instruction is enabled by the One Chip Emulator OCE then the break mode is activated If SBRK is not enabled by the OCE then the hardware trap soft break Class A Vector...

Page 300: ...2 SP tmp1 op1 tmp2 Description Switches contexts of any register Switching context is a push and load operation The contents of the register specified by the first operand op1 are pushed onto the stac...

Page 301: ...f times as specified by the source operand op2 The least significant bits of the result are filled with zeros accordingly The most significant bit is shifted into the Carry Only shift values between 0...

Page 302: ...User Manual C166S V2 Detailed Instruction Description User Manual 8 302 V 1 7 2001 01 Encoding Mnemonic Format Bytes SHL Rwn data4 5C n 2 SHL Rwn Rwm 4C nm 2...

Page 303: ...Since the bits shifted out effectively represent the remainder the Overflow flag is used instead as a Rounding flag A shift right is a division by a power of two The overflow flag with the carry flag...

Page 304: ...7 2001 01 C The carry flag is set according to the last least significant bit shifted out of op1 Cleared for a shift count of zero N Set if the most significant bit of the result is set Cleared otherw...

Page 305: ...scription This instruction is used to perform a software reset A software reset has the same effect on the microcontroller as an externally applied hardware reset To ensure that this instruction is no...

Page 306: ...th a preset value and clears the low byte After this instruction has been executed and if the WDTCTL bit of the CPUCON1 register is cleared the Watchdog Timer cannot be disabled regardless of the exec...

Page 307: ...ags E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmetic un...

Page 308: ...E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmetic under...

Page 309: ...perform multiple precision arithmetic CPU Flags E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zer...

Page 310: ...orm multiple precision arithmetic CPU Flags E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero and...

Page 311: ...The invoked routine is determined by branching to the specified vector table entry point This routine has no indication of whether it was called by software or hardware System state is preserved iden...

Page 312: ...User Manual C166S V2 Detailed Instruction Description User Manual 8 312 V 1 7 2001 01 Encoding Mnemonic Format Bytes TRAP trap7 9B t ttt0 2...

Page 313: ...perand specified by op1 The result is then stored in op1 CPU Flags E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if...

Page 314: ...and specified by op1 The result is then stored in op1 CPU Flags E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if re...

Page 315: ...User Manual C166S V2 Detailed Instruction Description User Manual 8 315 V 1 7 2001 01 8 2 DSP Instruction Set...

Page 316: ...bit ACC contents MAC Flags MV Set if the ACC contents was 80 0000 0000H Cleared otherwise MSL Set if the contents of ACC is automatically saturated Not affected otherwise ME Set if the MAE is used Cl...

Page 317: ...bit operand is a sign extended result of the concatenation of the two source operands op1 LSW and op2 MSW MAC Flags MV Always cleared MSL Set if the contents of ACC is automatically saturated Not aff...

Page 318: ...W and op2 MSW MAC Flags MV Set if an arithmetic overflow occurred i e the result cannot be represented in the 40 bit data type Cleared otherwise MSL Set if the contents of ACC is automatically saturat...

Page 319: ...n multiplied by two before being added to ACC register MAC Flags MV Set if an arithmetic overflow occurred i e the result cannot be represented in the 40 bit data type Cleared otherwise MSL Set if the...

Page 320: ...with sign 0 if the original most significant bit was a 0 or with sign 1 if the original most significant bit was 1 Only shift values from 0 to 16 inclusive are allowed op1 can be either a 5 bit unsig...

Page 321: ...l C166S V2 Detailed Instruction Description User Manual 8 321 V 1 7 2001 01 Encoding Mnemonic Format Bytes CoASHR data5 rnd A3 00 B2 rrr 4 CoASHR Rwn rnd A3 nn BA rrr0 0000 4 CoASHR Rwm rnd 83 mm BA r...

Page 322: ...illed with sign 0 if the original most significant bit was a 0 or with sign 1 if the original most significant bit was 1 Only shift values from 0 to 16 inclusive are allowed op1 can be either a 5 bit...

Page 323: ...Manual C166S V2 Detailed Instruction Description User Manual 8 323 V 1 7 2001 01 Encoding Mnemonic Format Bytes CoASHR data5 A3 00 A2 rrr 4 CoASHR Rwn A3 nn AA rrr0 0000 4 CoASHR Rwm 83 mm AA rrr0 0q...

Page 324: ...gn extended result of the concatenation of the two source operands op1 LSW and op2 MSW The MS bit of the MCW register does not affect the result MAC Flags MV Set if the ACC contents are strictly less...

Page 325: ...source operand The 40 bit source operand is the sign extended result of the concatenation of the two source operands op1 LSW and op2 MSW MAC Flags MV Always cleared MSL Not affected ME Always cleared...

Page 326: ...ource operands op1 LSW and op2 MSW The 40 bit source operand is 2s complemented before being stored in the ACC register MAC Flags MV Always cleared MSL Set if the contents of ACC is automatically satu...

Page 327: ...ion of the two source operands op1 LSW and op2 MSW The 40 bit operand is also multiplied by two before being stored in the ACC register MAC Flags MV Always cleared MSL Set if the contents of ACC is au...

Page 328: ...operands op1 LSW and op2 MSW The 40 bit operand is also multiplied by two and negated before being stored in the ACC register MAC Flags MV Always cleared MSL Set if the contents of ACC is automatical...

Page 329: ...e MP flag is set it is one bit left shifted then it is added to the 40 bit ACC register contents Finally the result is 2s complement rounded before being stored in the 40 bit ACC register The MAL regi...

Page 330: ...V2 Detailed Instruction Description User Manual 8 330 V 1 7 2001 01 Encoding Mnemonic Format Bytes CoMAC Rwn Rwm rnd A3 nm D1 rrr0 0000 4 CoMAC Rwn Rwm rnd 83 nm D1 rrr0 0qqq 4 CoMAC IDXi Rwm rnd 93...

Page 331: ...d then if the MP flag is set it is one bit left shifted then it is added to the 40 bit ACC register contents before being stored in the 40 bit ACC register MAC Flags MV Set if an arithmetic overflow o...

Page 332: ...C166S V2 Detailed Instruction Description User Manual 8 332 V 1 7 2001 01 Encoding Mnemonic Format Bytes CoMAC Rwn Rwm A3 nm D0 rrr0 0000 4 CoMAC Rwn Rwm 83 nm D0 rrr0 0qqq 4 CoMAC IDXi Rwm 93 Xm D0...

Page 333: ...n if the MP flag is set it is one bit left shifted then it is subtracted from the 40 bit ACC register contents before being stored in the 40 bit ACC register MAC Flags MV Set if an arithmetic underflo...

Page 334: ...C166S V2 Detailed Instruction Description User Manual 8 334 V 1 7 2001 01 Encoding Mnemonic Format Bytes CoMAC Rwn Rwm A3 nm E0 rrr0 0000 4 CoMAC Rwn Rwm 83 nm E0 rrr0 0qqq 4 CoMAC IDXi Rwm 93 Xm E0...

Page 335: ...e 40 bit ACC register contents Finally the result is 2s complement rounded before being stored in the 40 bit ACC register The MAL register is cleared In parallel to the arithmetic operation and to the...

Page 336: ...S V2 Detailed Instruction Description User Manual 8 336 V 1 7 2001 01 MN Set if the most significant bit of the result is set Cleared otherwise Encoding Mnemonic Format Bytes CoMACM IDXi Rwm rnd 93 Xm...

Page 337: ...ontents before being stored in the 40 bit ACC register In parallel to the arithmetic operation and to the two parallel reads the data pointed to by IDXi overwrites another data located in memory DPRAM...

Page 338: ...User Manual C166S V2 Detailed Instruction Description User Manual 8 338 V 1 7 2001 01 Encoding Mnemonic Format Bytes CoMACM IDXi Rwm 93 Xm D8 rrr0 0qqq 4...

Page 339: ...contents before being stored in the 40 bit ACC register In parallel to the arithmetic operation and to the two parallel reads the data pointed to by IDXi overwrites another data located in memory DPR...

Page 340: ...User Manual C166S V2 Detailed Instruction Description User Manual 8 340 V 1 7 2001 01 Encoding Mnemonic Format Bytes CoMACM IDXi Rwm 93 Xm E8 rrr0 0qqq 4...

Page 341: ...e 40 bit ACC register contents are subtracted from the result Finally the result is 2s complement rounded before being stored in the 40 bit ACC register The MAL register is cleared In parallel to the...

Page 342: ...n Description User Manual 8 342 V 1 7 2001 01 MZ Set if result equals zero Cleared otherwise MN Set if the most significant bit of the result is set Cleared otherwise Encoding Mnemonic Format Bytes Co...

Page 343: ...from the result before being stored in the 40 bit ACC register In parallel to the arithmetic operation and to the two parallel reads the data pointed to by IDXi overwrites another data located in memo...

Page 344: ...User Manual C166S V2 Detailed Instruction Description User Manual 8 344 V 1 7 2001 01 Encoding Mnemonic Format Bytes CoMACMR IDXi Rwm 93 Xm F8 rrr0 0qqq 4...

Page 345: ...s 2s complement rounded before being stored in the 40 bit ACC register The MAL register is cleared In parallel to the arithmetic operation and to the two parallel reads the data pointed to by IDXi ove...

Page 346: ...User Manual C166S V2 Detailed Instruction Description User Manual 8 346 V 1 7 2001 01 Encoding Mnemonic Format Bytes CoMACMRsu IDXi Rwm rnd 93 Xm 79 rrr0 0qqq 4...

Page 347: ...to the arithmetic operation and to the two parallel reads the data pointed to by IDXi overwrites another data located in memory DPRAM The address of the overwritten data depends on the operation exec...

Page 348: ...stored in the 40 bit ACC register The MAL register is cleared In parallel to the arithmetic operation and to the two parallel reads the data pointed to by IDXi overwrites another data located in memo...

Page 349: ...User Manual C166S V2 Detailed Instruction Description User Manual 8 349 V 1 7 2001 01 Encoding Mnemonic Format Bytes CoMACMRu IDXi Rwm rnd 93 Xm 39 rrr0 0qqq 4...

Page 350: ...hmetic operation and to the two parallel reads the data pointed to by IDXi overwrites another data located in memory DPRAM The address of the overwritten data depends on the operation executed on IDXi...

Page 351: ...before being stored in the 40 bit ACC register The MAL register is cleared In parallel to the arithmetic operation and to the two parallel reads the data pointed to by IDXi overwrites another data loc...

Page 352: ...User Manual C166S V2 Detailed Instruction Description User Manual 8 352 V 1 7 2001 01 Encoding Mnemonic Format Bytes CoMACMRus IDXi Rwm rnd 93 Xm B9 rrr0 0qqq 4...

Page 353: ...to the arithmetic operation and to the two parallel reads the data pointed to by IDXi overwrites another data located in memory DPRAM The address of the overwritten data depends on the operation exec...

Page 354: ...eing stored in the 40 bit ACC register The MAL register is cleared In parallel to the arithmetic operation and to the two parallel reads the data pointed to by IDXi overwrites another data located in...

Page 355: ...User Manual C166S V2 Detailed Instruction Description User Manual 8 355 V 1 7 2001 01 Encoding Mnemonic Format Bytes CoMACMsu IDXi Rwm rnd 93 Xm 59 rrr0 0qqq 4...

Page 356: ...arithmetic operation and to the two parallel reads the data pointed to by IDXi overwrites another data located in memory DPRAM The address of the overwritten data depends on the operation executed on...

Page 357: ...e arithmetic operation and to the two parallel reads the data pointed to by IDXi overwrites another data located in memory DPRAM The address of the overwritten data depends on the operation executed o...

Page 358: ...in the 40 bit ACC register The MAL register is cleared In parallel to the arithmetic operation and to the two parallel reads the data pointed to by IDXi overwrites another data located in memory DPRAM...

Page 359: ...User Manual C166S V2 Detailed Instruction Description User Manual 8 359 V 1 7 2001 01 Encoding Mnemonic Format Bytes CoMACMu IDXi Rwm rnd 93 Xm 19 rrr0 0qqq 4...

Page 360: ...peration and to the two parallel reads the data pointed to by IDXi overwrites another data located in memory DPRAM The address of the overwritten data depends on the operation executed on IDXi MAC Fla...

Page 361: ...operation and to the two parallel reads the data pointed to by IDXi overwrites another data located in memory DPRAM The address of the overwritten data depends on the operation executed on IDXi MAC F...

Page 362: ...unded before being stored in the 40 bit ACC register In parallel to the arithmetic operation and to the two parallel reads the data pointed to by IDXi overwrites another data located in memory DPRAM T...

Page 363: ...User Manual C166S V2 Detailed Instruction Description User Manual 8 363 V 1 7 2001 01 Encoding Mnemonic Format Bytes CoMACMus IDXi Rwm rnd 93 Xm 99 rrr0 0qqq 4...

Page 364: ...arithmetic operation and to the two parallel reads the data pointed to by IDXi overwrites another data located in memory DPRAM The address of the overwritten data depends on the operation executed on...

Page 365: ...e arithmetic operation and to the two parallel reads the data pointed to by IDXi overwrites another data located in memory DPRAM The address of the overwritten data depends on the operation executed o...

Page 366: ...is set it is one bit left shifted then the 40 bit ACC register contents are subtracted from the result Finally the result is 2s complement rounded before being stored in the 40 bit ACC register The MA...

Page 367: ...2 Detailed Instruction Description User Manual 8 367 V 1 7 2001 01 Encoding Mnemonic Format Bytes CoMACR Rwn Rwm rnd A3 nm F1 rrr0 0000 4 CoMACR Rwn Rwm rnd 83 nm F1 rrr0 0qqq 4 CoMACR IDXi Rwm rnd 93...

Page 368: ...f the MP flag is set it is one bit left shifted then the 40 bit ACC register contents are subtracted from the result before being stored in the 40 bit ACC register MAC Flags MV Set if an arithmetic un...

Page 369: ...166S V2 Detailed Instruction Description User Manual 8 369 V 1 7 2001 01 Encoding Mnemonic Format Bytes CoMACR Rwn Rwm A3 nm F0 rrr0 0000 4 CoMACR Rwn Rwm 83 nm F0 rrr0 0qqq 4 CoMACR IDXi Rwm 93 Xm F0...

Page 370: ...the 40 bit ACC register contents are subtracted from the result Finally the result is 2s complement rounded before being stored in the 40 bit ACC register The MAL register is cleared MAC Flags MV Set...

Page 371: ...etailed Instruction Description User Manual 8 371 V 1 7 2001 01 Encoding Mnemonic Format Bytes CoMACRsu Rwn Rwm rnd A3 nm 71 rrr0 0000 4 CoMACRsu Rwn Rwm rnd 83 nm 71 rrr0 0qqq 4 CoMACRsu IDXi Rwm rnd...

Page 372: ...from the result before being stored in the 40 bit ACC register MAC Flags MV Set if an arithmetic underflow occurred i e the result cannot be represented in the 40 bit data type Cleared otherwise MSL S...

Page 373: ...complement rounded before being stored in the 40 bit ACC register The MAL register is cleared MAC Flags MV Set if an arithmetic underflow occurred i e the result cannot be represented in the 40 bit d...

Page 374: ...lt before being stored in the 40 bit ACC register MAC Flags MV Set if an arithmetic underflow occurred i e the result cannot be represented in the 40 bit data type Cleared otherwise MSL Set if the con...

Page 375: ...the 40 bit ACC register contents are subtracted from the result Finally the result is 2s complement rounded before being stored in the 40 bit ACC register The MAL register is cleared MAC Flags MV Set...

Page 376: ...etailed Instruction Description User Manual 8 376 V 1 7 2001 01 Encoding Mnemonic Format Bytes CoMACRus Rwn Rwm rnd A3 nm B1 rrr0 0000 4 CoMACRus Rwn Rwm rnd 83 nm B1 rrr0 0qqq 4 CoMACRus IDXi Rwm rnd...

Page 377: ...the result before being stored in the 40 bit ACC register MAC Flags MV Set if an arithmetic underflow occurred i e the result cannot be represented in the 40 bit data type Cleared otherwise MSL Set i...

Page 378: ...complement rounded before being stored in the 40 bit ACC register The MAL register is cleared MAC Flags MV Set if an arithmetic overflow occurred i e the result cannot be represented in the 40 bit da...

Page 379: ...ts before being stored in the 40 bit ACC register MAC Flags MV Set if an arithmetic overflow occurred i e the result cannot be represented in the 40 bit data type Cleared otherwise MSL Set if the cont...

Page 380: ...ents before being stored in the 40 bit ACC register MAC Flags MV Set if an arithmetic underflow occurred i e the result cannot be represented in the 40 bit data type Cleared otherwise MSL Set if the c...

Page 381: ...t rounded before being stored in the 40 bit ACC register The MAL register is cleared MAC Flags MV Set if an arithmetic overflow occurred i e the result cannot be represented in the 40 bit data type Cl...

Page 382: ...being stored in the 40 bit ACC register MAC Flags MV Set if an arithmetic overflow occurred i e the result cannot be represented in the 40 bit data type Cleared otherwise MSL Set if the contents of AC...

Page 383: ...e being stored in the 40 bit ACC register MAC Flags MV Set if an arithmetic underflow occurred i e the result cannot be represented in the 40 bit data type Cleared otherwise MSL Set if the contents of...

Page 384: ...2s complement rounded before being stored in the 40 bit ACC register The MAL register is cleared MAC Flags MV Set if an arithmetic overflow occurred i e the result cannot be represented in the 40 bit...

Page 385: ...ts before being stored in the 40 bit ACC register MAC Flags MV Set if an arithmetic overflow occurred i e the result cannot be represented in the 40 bit data type Cleared otherwise MSL Set if the cont...

Page 386: ...ents before being stored in the 40 bit ACC register MAC Flags MV Set if an arithmetic underflow occurred i e the result cannot be represented in the 40 bit data type Cleared otherwise MSL Set if the c...

Page 387: ...nded If the contents of the 40 bit ACC register are smaller than the 40 bit operand then the ACC register is loaded with it Otherwise the ACC register remains unchanged The MS bit of the MCW register...

Page 388: ...contents of the ACC register are greater than the 40 bit operand then the ACC register is loaded with it Otherwise the ACC register remains unchanged The MS bit of the MCW register does not affect th...

Page 389: ...instructions IDXi can address the entire memory This instruction does not affect the Mac Flags but modifies the CPU Flags as any other MOV instruction Note CoMOV is the only MAC instruction which affe...

Page 390: ...ulting signed 32 bit product is first sign extended then if the MP flag is set it is one bit left shifted Finally the result is 2s complement rounded before being stored in the 40 bit ACC register The...

Page 391: ...V2 Detailed Instruction Description User Manual 8 391 V 1 7 2001 01 Encoding Mnemonic Format Bytes CoMUL Rwn Rwm rnd A3 nm C1 rrr0 0000 4 CoMUL Rwn Rwm rnd 83 nm C1 rrr0 0qqq 4 CoMUL IDXi Rwm rnd 93...

Page 392: ...op2 The resulting signed 32 bit product is first sign extended then if the MP flag is set it is one bit left shifted before being stored in the 40 bit ACC register MAC Flags MV Always cleared MSL Not...

Page 393: ...C166S V2 Detailed Instruction Description User Manual 8 393 V 1 7 2001 01 Encoding Mnemonic Format Bytes CoMUL Rwn Rwm A3 nm C0 rrr0 0000 4 CoMUL Rwn Rwm 83 nm C0 rrr0 0qqq 4 CoMUL IDXi Rwm 93 Xm C0...

Page 394: ...d op2 The resulting signed 32 bit product is first sign extended then if the MP flag is set it is one bit left shifted and finally it is negated before being stored in the 40 bit ACC register MAC Flag...

Page 395: ...op1 and op2 respectively The resulting signed 32 bit product is first sign extended then it is rounded before being stored in the 40 bit ACC register The MAL register is cleared MAC Flags MV Always c...

Page 396: ...source operands op1 and op2 respectively The resulting signed 32 bit product is first sign extended before being stored in the 40 bit ACC register MAC Flags MV Always cleared MSL Not affected ME Alway...

Page 397: ...perands op1 and op2 respectively The resulting signed 32 bit product is first sign extended then is negated before being stored in the 40 bit ACC register MAC Flags MV Always cleared MSL Not affected...

Page 398: ...The resulting unsigned 32 bit product is first zero extended then it is rounded before being stored in the 40 bit ACC register The MAL register is cleared MAC Flags MV Always cleared MSL Set if the co...

Page 399: ...ds op1 and op2 The resulting unsigned 32 bit product is zero extended before being stored in the 40 bit ACC register MAC Flags MV Always cleared MSL Set if the contents of ACC is automatically saturat...

Page 400: ...bit product is first zero extended then it is negated before being stored in the 40 bit ACC register MAC Flags MV Always cleared MSL Set if the contents of ACC is automatically saturated Not affected...

Page 401: ...nds op1 and op2 respectively The resulting signed 32 bit product is first sign extended then it is rounded before being stored in the 40 bit ACC register The MAL register is cleared MAC Flags MV Alway...

Page 402: ...source operands op1 and op2 respectively The resulting signed 32 bit product is first sign extended before being stored in the 40 bit ACC register MAC Flags MV Always cleared MSL Not affected ME Alway...

Page 403: ...rands op1 and op2 respectively The resulting signed 32 bit product is first sign extended then it is negated before being stored in the 40 bit ACC register MAC Flags MV Always cleared MSL Not affected...

Page 404: ...Flags MV Set if an arithmetic underflow occurred i e the result cannot be represented in the 40 bit data type Cleared otherwise MSL Set if the contents of ACC is automatically saturated Not affected...

Page 405: ...C register The MAL register is cleared MAC Flags MV Set if an arithmetic underflow occurred i e the result cannot be represented in the 40 bit data type Cleared otherwise MSL Set if the contents of AC...

Page 406: ...Destination Operand s none Operation No Operation Description Modifies the address pointers MAC Flags MV Not affected MSL Not affected ME Not affected MSV Not affected MC Not affected MZ Not affected...

Page 407: ...r MAL is cleared Note CoRND is a shortname for CoASHR 0 rnd MAC Flags MV Set if an arithmetic overflow occurred i e the result cannot be represented in the 40 bit data type Cleared otherwise MSL Set i...

Page 408: ...rom 0 to 16 inclusive are allowed op1 can be either a 5 bit unsigned immediate data the shift range is from 0 to 16 in this case or the four least significant bits the shift range is from 0 to 15 in t...

Page 409: ...n Description User Manual 8 409 V 1 7 2001 01 MN Set if the most significant bit of the result is set Cleared otherwise Encoding Mnemonic Format Bytes CoSHL data5 A3 00 82 rrr 4 CoSHL Rwn A3 nn 8A rrr...

Page 410: ...cant bits of the result are filled with zeros accordingly Only shift values from 0 to 16 inclusive are allowed op1 can be either a 5 bit unsigned immediate data the shift range is from 0 to 16 in this...

Page 411: ...r Manual C166S V2 Detailed Instruction Description User Manual 8 411 V 1 7 2001 01 Encoding Mnemonic Format Bytes CoSHR data5 A3 00 92 rrr 4 CoSHR Rwn A3 nn 9A rrr0 0000 4 CoSHR Rwm 83 mm 9A rrr0 0qqq...

Page 412: ...Operation op1 op2 Description Moves the contents of a MAC Unit register specified by the source operand op2 to the location specified by the destination operand op1 MAC Flags MV Not affected MSL Not a...

Page 413: ...W and op2 MSW MAC Flags MV Set if an arithmetic underflow occurred i e the result cannot be represented in the 40 bit data type Cleared otherwise MSL Set if the contents of ACC is automatically satura...

Page 414: ...tiplied by two before being subtracted from the ACC register MAC Flags MV Set if an arithmetic underflow occurred i e the result cannot be represented in the 40 bit data type Cleared otherwise MSL Set...

Page 415: ...tiplied by two before being subtracted from the ACC register MAC Flags MV Set if an arithmetic underflow occurred i e the result cannot be represented in the 40 bit data type Cleared otherwise MSL Set...

Page 416: ...W and op2 MSW MAC Flags MV Set if an arithmetic underflow occurred i e the result cannot be represented in the 40 bit data type Cleared otherwise MSL Set if the contents of ACC is automatically satura...

Page 417: ...rand symbol size comment mem24 MM2 MM0 MM1 24 direct 24 bit address for memory access The format MM2 MM0 MM1 means that the 24 bit address byte2 byte1 byte0 has to be presented in the order byte2 byte...

Page 418: ...OLOADB Rbx banksel2 6D ss00 x 00 00 1 reads byte from GPR and writes to OCDS OSTOREB Rbx banksel2 7D ss00 x 00 00 1 reads byte from OCDS and writes to GPR MOVCSIP data23 9D dd dd d ddd0 1 writes CSP I...

Page 419: ...mory and writes result to trace bus TLOAD Rx banksel2 CA ss00 x 00 00 1 reads GPR and writes result to trace bus INOP 9A 00 00 00 AA 00 00 00 BA 00 00 00 DA 00 00 00 EA 00 00 00 FA 00 00 00 1 injected...

Page 420: ...User Manual C166S V2 Detailed Instruction Description User Manual 8 420 V 1 7 2001 01...

Page 421: ...addressable Table 9 1 Addressing Modes to Access Word GPRs Name Physical Address 1 1 Addressing mode only usable if the GPR bank is memory mapped 8 Bit Address 4 Bit Address Description Reset Value R0...

Page 422: ...3 GPR access via ESFR area 8 Bit Address 4 Bit Address Description Reset Value RL0 CP 0 F0H 0h General Purpose Byte Register RL0 UUH RH0 CP 1 F1H 1h General Purpose Byte Register RL1 UUH RL1 CP 2 F2H...

Page 423: ...ister 03 H 1 CSP FE08H 04H Code Segment Pointer 8 bits not directly writable 0000H DPP0 FE00H 00H Data Page Pointer 0 10 bits 0000H DPP1 FE02H 01H Data Page Pointer 1 10 bits 0001H DPP2 FE04H 02H Data...

Page 424: ...6H Trap Flag Register 0000H VECSEG b FF12H 89H Vector Table Segment Register H 2 ZEROS b FF1CH 8EH Constant Value 0 s Register read only 0000H 1 defined by reset configuration 2 defined by reset confi...

Page 425: ...mulator High Word 0000H IDX0 b FF08H 84H MAC Address Pointer 0 0000H IDX1 b FF0AH 85H MAC Address Pointer 1 0000H SPSEG b FF0CH 86H Stack Pointer Segment Register 0000H MDC b FF0EH 87H Multiply Divide...

Page 426: ...nel 0 Destination Pointer 0000H DSTP1 EC46H PEC Channel 1 Destination Pointer 0000H DSTP2 EC4AH PEC Channel 2 Destination Pointer 0000H DSTP3 EC4EH PEC Channel 3 Destination Pointer 0000H DSTP4 EC52H...

Page 427: ...ess Reg 0000H PECSEG2 EC84H PEC Pointer 2 Segment Address Reg 0000H PECSEG3 EC86H PEC Pointer 3 Segment Address Reg 0000H PECSEG4 EC88H PEC Pointer 4 Segment Address Reg 0000H PECSEG5 EC8AH PEC Pointe...

Page 428: ...Source Pointer 0000H DSTP1 EC46H PEC Channel 1 Destination Pointer 0000H SRCP2 EC48H PEC Channel 2 Source Pointer 0000H DSTP2 EC4AH PEC Channel 2 Destination Pointer 0000H SRCP3 EC4CH PEC Channel 3 So...

Page 429: ...hannel 2 Control Register 0000H PECC3 FEC6H 63H PEC Channel 3 Control Register 0000H PECC4 FEC8H 64H PEC Channel 4 Control Register 0000H PECC5 FECAH 65H PEC Channel 5 Control Register 0000H PECC6 FEC...

Page 430: ...of EBC Pins 00F0H EBCMOD1 EE02H Global Behavior of EBC 0000H FCONCS0 EE12H Function Control for CS0 0021H FCONCS1 EE1AH Function Control for CS1 0000H FCONCS2 EE22H Function Control for CS2 0000H FCON...

Page 431: ...TCONCS2 EE20H Timing Control for CS2 0000H FCONCS2 EE22H Function Control for CS2 0000H ADDRSEL2 EE26H Address Window Selection for CS2 0000H TCONCS3 EE28H Timing Control for CS3 0000H FCONCS3 EE2AH...

Page 432: ...User Manual C166S V2 Summary of CPU Subsystem Registers User Manual 9 432 V 1 7 2001 01...

Page 433: ...ter 423 425 Cycle counts 194 D Data Page Boundaries 99 Data Page Pointer 49 Data Types 68 DMU 12 E EBC 13 End of PEC Interrupt Sub Node 143 External Bus Controller 13 External Bus Idle State 169 Exter...

Page 434: ...CoMACMsu 357 CoMACMu 358 360 CoMACMu 361 CoMACMus 362 364 CoMACMus 365 CoMACR 366 368 CoMACRsu 370 372 CoMACRu 373 374 CoMACRus 375 377 CoMACsu 378 379 CoMACsu 380 CoMACu 381 382 CoMACu 383 CoMACus 38...

Page 435: ...t Control Register 140 Interrupt Jump Table Cache 125 Interrupt System 118 J JTAG 13 M MAH Register 423 425 MAL Register 423 425 MCW Register 423 425 MDC Register 423 425 MDH Register 423 425 MDL Regi...

Page 436: ...423 425 MRW 423 425 MSW 423 425 ONES 423 425 PSW 423 425 QR0 424 QR1 424 QX0 423 424 QX1 424 SP 424 425 SPSEG 424 425 STKOV 424 425 STKUN 424 425 TFR 424 425 VECSEG 424 425 xxIC 140 ZEROS 424 425 Res...

Page 437: ...437...

Page 438: ...es and clearly defined processes which are both constantly under review and ultimately lead to good operating results Better operating results and business excellence mean less idleness and wastefulne...

Page 439: ...iew Pricing Inventory Delivery Lifecycle Information Infineon SAFXC164CS16F40FBB SAF XC164CS 16F40F BB SAK XC164CS 16F20F BB SAK XC164CS 16F40F BB SAF XC164CS 16F20F BB FX164CS16F40FBBXP XC164CS16F40F...

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