Infineon Technologies C166S V2, User Manual

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User Manual
C166S V2
Summary of CPU/Subsystem Registers
User Manual 9-422 V 1.7, 2001-01
The first 8 GPRs (R7...R0) may be also accessed bytewise. Unlike SFRs, writing to a
GPR byte does not affect another byte of the GPR.
The following byte-accessible registers have special names.
Table 9-2 Addressing Modes to Access Byte–GPRs
Name Physical
Address
1)
1)
Addressing mode only usable if the GPR bank is memory mapped.
The 8-bit short addresses F0
H
...FE
H
within the ESFR area are reserved and provide
access to the current register bank via short register addressing modes. The
GPRs are mirrored to the ESFR area which allows access to the current register
bank even after switching register spaces (see example below).
MOV R5, DP3 ;GPR access via SFR area
EXTR #1
MOV R5, ODP3 ;GPR access via ESFR area
8-Bit
Address 4-Bit
Address Description Reset
Value
RL0 (CP)+0 F0
H
0h General Purpose Byte Register RL0 UU
H
RH0 (CP)+1 F1
H
1h General Purpose Byte Register RL1 UU
H
RL1 (CP)+2 F2
H
2h General Purpose Byte Register RL2 UU
H
RH1 (CP)+3 F3
H
3h General Purpose Byte Register RL3 UU
H
RL2 (CP)+4 F4
H
4h General Purpose Byte Register RL4 UU
H
RH2 (CP)+5 F5
H
5h General Purpose Byte Register RL5 UU
H
RL3 (CP)+6 F6
H
6h General Purpose Byte Register RL6 UU
H
RH3 (CP)+7 F7
H
7h General Purpose Byte Register RL7 UU
H
RL4 (CP)+8 F8
H
8h General Purpose Byte Register RL8 UU
H
RH4 (CP)+9 F9
H
9h General Purpose Byte Register RL9 UU
H
RL5 (CP)+10 FA
H
Ah General Purpose Byte Register RL10 UU
H
RH5 (CP)+11 FB
H
Bh General Purpose Byte Register RL11 UU
H
RL6 (CP)+12 FC
H
Ch General Purpose Byte Register RL12 UU
H
RH6 (CP)+13 FD
H
Dh General Purpose Byte Register RL13 UU
H
RL7 (CP)+14 FE
H
Eh General Purpose Byte Register RL14 UU
H
RH7 (CP)+15 FF
H
Fh General Purpose Byte Register RL15 UU
H