Infineon Technologies C166S V2, User Manual

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User Manual
C166S V2
Central Processing Unit
User Manual 2-16 V 1.7, 2001-01
The new core architecture of the C166S V2 CPU results in higher CPU clock frequencies
and reduces the number of clock cycles per executed instruction by half, compared to
the C166 core. C166S V2 CPU also integrates a multiplication and accumulation unit
which dramatically increases performance of the DSP-intensive tasks.
C166S V2 CPU has eight main units that are listed below. All of these units have been
optimized to achieve maximum performance and flexibility.
• High Performance I nstruction F etch U nit ( IFU )
– High Bandwidth Fetch Interface
– Instruction FIFO
– High Performance Branch-, Call-, and Loop-Processing with instruction flow
prediction
• Return Stack
– Injection/Exception Handler
– Handling of Interrupt Requests
– Handling of Hardware Failures
• I nstruction Pip eline ( IPIP )
– Bypassable 2-stage Prefetch Pipeline
– 5-stage Execution Pipeline
• A ddress and D ata U nit ( ADU )
– 16-bit arithmetic unit for address generation
– DSP address unit with a set of dedicated address- and offset pointers
• A rithmetic and L ogic U nit ( ALU )
– 8-bit and 16-bit Arithmetic Unit
– 16-bit Barrel Shifter
– Multiplication and Division Unit
– 8-bit and 16-bit Logic Unit
– Bit manipulation Unit
• M ultiply and AC cumulate Unit ( MAC )
– 16-bit multiplier with 32-bit result generation
1)
– 40-bit Accumulator with 40-bit Barrel Shifter
– Repeat Control Unit
• R egister F ile ( RF )
– 5-port Register File with three independent register banks
• W rite B ack B uffer ( WB )
– 3-entries buffer
1)
The same hardware-multiplier is used in the ALU and in the MAC Unit.