Infineon Technologies C166S V2, User Manual

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User Manual
C166S V2
Central Processing Unit
User Manual 2-47 V 1.7, 2001-01
be addressed via ’reg’. Note that the high byte of an SFR cannot be accessed
via the ’reg’ addressing mode. Short ’reg’ addresses in the range from F0
H
to
FF
H
always specify GPRs. In that case, only the lower four bits of ’reg’ are sig-
nificant for physical address generation and, therefore, it is identical to the
address generation described for the ’Rb’ and ’Rw’ addressing modes.
bitoff: Specifies direct access to any word in the bit addressable memory space. The
’bitoff’ value requires eight bits in the instruction format. Depending on the
specified ’bitoff’ range different base addresses are used to generate physical
addresses: Short ’bitoff’ addresses in the range from 00
H
to 7F
H
use
00’FD00
H
as a base address to specify the 128 highest internal RAM word
locations in the range from 00’FD00
H
h to 00’FDFE
H
. Short 'bitoff' addresses in
the range from 80
H
to EF
H
use base address 00’FF00
H
to specify the internal
SFR word locations in the range from 00’FF00
H
to 00’FFDE
H
or base address
00’F100
H
to specify the internal ESFR word locations in the range from
00’F100
H
to 00’F1DE
H
. The ‘bitoff’ accesses to the ESFR area require a pre-
ceding EXT*R instruction to switch the base address. For short 'bitoff'
addresses from F0
H
to FF
H
, only the lowest four bits are used to generate the
address of the selected word GPR.
bitaddr: Any bit address is specified by a word address within the bit addressable
memory space (see 'bitoff'), and by a bit position ('bitpos') within that word.
Therefore, 'bitaddr' requires twelve bits in the instruction format.