Infineon Technologies C166S V2, User Manual

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User Manual
C166S V2
C166S V2 Memory Organization
User Manual 3-96 V 1.7, 2001-01
3.3.2 Special Function Register Areas
The functions of the CPU, the bus interface, the IO ports, and the on-chip peripherals of
the C166S V2 device are controlled via a number of so-called Special Function
Registers (SFRs). These SFRs are arranged within two areas of 512 Bytes each. The
first register block, the SFR area, is located in the 512 Bytes above the DPRAM
(00’FE00
H
...00’FFFF
H
). The second register block, the Extended SFR (ESFR) area, is
located in the 512 Bytes below the DPRAM (00’F000
H
...00’F1FF
H
).
Special Function Registers can be addressed via indirect and long 16-bit addressing
modes. Using an 8-bit offset together with an implicit base address allows word SFRs
and their respective low bytes to be addressed. However, this
does not work for the
respective high bytes!
Note: High byte access of SFRs using the 8-bit offset addressing mode is not possible.
Note: Writing to any byte of an SFR causes the non-addressed complementary byte to
be cleared!
Note: GPRs can be accessed using the 8-bit offset addressing mode, but they are not
mapped into the SFR and ESFR memory area. an internal peripheral bus access
is executed using the respective long address instead of a GPR access.
The upper half of each register block (except the 16 highest words, refer to Section 2.5.1
) is bit-addressable, so the respective control/status bits can be directly modified or
checked using bit addressing.
When accessing registers in the ESFR area using 8-bit addresses or direct bit
addressing, the Extend Register (EXTR) instruction is required to switch the short
addressing mechanism from the standard SFR area to the Extended SFR area before
accessing registers in the ESFR area. This is not required for 16-bit and indirect
addresses. GPRs R15...R0 are duplicated, i.e. they are accessible within both register
blocks via short 2-, 4- or 8-bit addresses without switching.
Example:
EXTR #4 ;Switch to ESFR area for the next four instructions
MOV ODP2, #data16 ;ODP2 (ESFR register) uses 8-bit register addressing
BFLDL DP6, #mask, #data8;DP6 (ESFR register) bit addressing for bit fields
BSET
DP6.7 ;DP6 (ESFR register) bit addressing for single bits
MOV T8REL, R1 ;T8REL uses 16-bit address, R1 is duplicatedº
;...and also accessible via the ESFR mode
;(EXTR is not required for this access)
;------- ;------------------- ;The scope of the EXTR #4 instruction ends here!
MOV T8REL, R1 ;T8REL uses 16-bit address, R1 is duplicatedº
;...and does not require switching