Infineon Technologies C166S V2, User Manual

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User Manual
C166S V2
Interrupt and Exception Handling
User Manual 5-119 V 1.7, 2001-01
Figure 5-1 Block Diagram of the Interrupt and PEC Controller
Interrupt and Peripheral Event Controller
Interrupt
Request
Lines
irq0
irq1
irq2
irq3
irq n-3
irq n-2
Arbitration
Arbitration
Control
(Interrupt
Control
Registers)
P eripheral
E vent
C ontroller
(PEC)
Arbitr.
Winner
PEC
Control
(PEC
Control
Registers)
irq0IC
irq1IC
irq126IC
PECC0
PECC1
PECC7
PEC Pointer
SRCP0
SRCP1
SRCP7
DSTP0
DSTP1
DSTP7
PECSEG0
PECSEG1
PECSEG7
Interrupt
Handler
Interrupt
Request
EOP
INT
2)
Interrupt
Handler
Control
EOPIC PECISNC
Fast Bank
Switching
BNKSEL0
BNKSEL3
Interrupt Jump
Table Cache
FINT0CSP
FINT0ADDR
FINT1CSP
FINT1ADDR
Injection
Control
(CPU Action
Request)
PEC Request
Interrupt
Request
Request
Control
C166S V2
CPU
In
je
cti
o
n
In
te
rf
a
c
e
OCE/
OCDS
End of PEC Interrupt (EOPINT) is connected to interrupt request line irq n-1.
Therefore, only n-1 interrupt lines (irq n-2...0) are available for peripheral request
handling.
2)
Request
Control
OCE
Injection
Request &
Control
irq n-1
1) number of interrupt nodes n (upto 128)
1)