Infineon Technologies C166S V2, User Manual

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User Manual
C166S V2
Instruction Pipeline
User Manual 4-108 V 1.7, 2001-01
two independent read/write ports; this allows parallel read and write operation without
delays. Write accesses to the internal SRAM can be buffered in a Write BACK Buffer until
read accesses are finished.
• Bandwidth conflicts in the DPRAM Area
All instructions except the CoXXX instructions can read only one memory operand per
cycle. A conflict between the read and one write access cannot occur because the
DPRAM has two independent read/write ports.
I
n-1
........
I
n
ADD op1,R1
I
n+1
ADD R6,R0
I
n+2
ADD R6,op2
I
n+3
MOV R3,[R0]
I
n+4
........
Note: Only other pipeline stall conditions can generate a DPRAM bandwidth conflict.
The DPRAM is a synchronous pipelined memory. The read access starts with the
valid addresses on the address stage. The data are delivered in the Memory
stage. If a memory read access is stalled in the Memory stage and the following
instruction on the Address stage tries to start a memory read, the new read access
must be delayed as well. But, this conflict is hidden by an already existing stall of
the pipeline.
T
n
T
n+1
T
n+2
T
n+3
T
n+4
T
n+5
DECODE I
n
=
ADD op1,R1
I
n+1
=
ADD R6,R0
I
n+2
=
ADD R6,op2
I
n+3
=
MOV R3,[R0]
I
n+4
I
n+5
ADDRESS I
n-1
I
n
=
ADD op1,R1
I
n+1
=
ADD R6,R0
I
n+2
=
ADD R6,op2
I
n+3
=
MOV R3,[R0]
I
n+4
MEMORY I
n-2
I
n-1
I
n
=
ADD op1,R1
I
n+1
=
ADD R6,R0
I
n+2
=
ADD R6,op2
I
n+3
=
MOV R3,[R0]
EXECUTE I
n-3
I
n-2
I
n-1
I
n
=
ADD op1,R1
I
n+1
=
ADD R6,R0
I
n+2
=
ADD R6,op2
WRITE BACK I
n-4
I
n-3
I
n-2
I
n-1
I
n
=
ADD op1,R1
I
n+1
=
ADD R6,R0