Infineon Technologies C166S V2, User Manual

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User Manual
C166S V2
C166S V2 Memory Organization
User Manual 3-99 V 1.7, 2001-01
3.5 Crossing Memory Boundaries
The address space of the C166S V2 CPU is implicitly divided into logical memory areas
and equally sized blocks of different granularity. Crossing the boundaries between these
areas or blocks (code or data) requires special attention to ensure that the controller
executes the desired operations.
Memory Areas are partitions of the address space that represent different kinds of
memory (if provided at all). These memory areas are the internal RAM areas, the internal
IO areas, the internal Program Memories (if available), and the external memory.
Accessing subsequent data locations that belong to different memory areas is not fully
supported and may therefore lead to erroneous results. There is no problem if the
memory boundaries are word aligned. However, when executing
code , the different
memory areas (Internal Program Memory areas and external memory) must be switched
explicitly via branch instructions. Sequential boundary crossing is not supported and may
leads to erroneous results.
Segments are contiguous blocks of 64 KBytes each. They are referenced via the Code
Segment Pointer (CSP) for code fetches and via an explicit segment number for data
accesses overriding the standard DPP scheme.
During code fetching, segments are not changed automatically, but rather must be
switched explicitly. The instructions JMPS, CALLS, and RETS will do this. Larger
sequential programs make sure that the highest used code location of a segment
contains an unconditional branch instruction to the respective following segment, to
prevent the prefetcher from trying to leave the current segment.
Data Pages are contiguous blocks of 16 KBytes each. They are referenced via the data
page pointers DPP3...0 and via an explicit data page number for data accesses
overriding the standard DPP scheme. Each DPP register can select one of the possible
1024 data pages. The DPP register that is used for the current access is selected via the
two upper bits of the 16-bit data address. Subsequent 16-bit data addresses that cross
the 16 KByte data page boundaries will use different data page pointers, while the
physical locations need not be subsequent within memory.
3.6 System Stack
The system stack may be defined within the internal RAM, but can be also located
externally. The size of the system stack is limited to 64 kBytes and must be located in
one segment. For all system stack operations, the stack memory is accessed via a 24 bit
stack pointer. The Stack Pointer register (SP) represents the low order 16 bits of the
24 bit stack pointer, also referred to as Stack Pointer Offset. The Stack Segment Pointer
(SPSEG) represents the high order 8 bits of the stack pointer, also referred to as Stack
Segment.
The system stack implementation in the C166S V2 CPU is from high to low memory. The
system stack grows downward as it is filled. The SP register is decremented first each