Infineon Technologies C166S V2, User Manual

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User Manual
C166S V2
Introduction
User Manual 1-14 V 1.7, 2001-01
Power Saving Control
The Power Saving Control block, known from the power management of the C166
derivatives, manages idle mode, power down mode, and sleep mode of the C166S V2.
ID Control
A set of six identification registers is defined for the most important silicon parameters,
including the chip manufacturer, the chip type and its properties. These ID registers can
be used for automatic test selection.
External Interrupt Control
The C166S V2 System provides asynchronous fast external interrupt inputs.
Central System Control
The central system behavior of the C166S V2 is controlled by this block. The frequency
of the PDBUS+ (bus clock) and of all peripherals connected to this bus is programmable
according to the maximum physical bus speed and the application requirements.
Furthermore, the clock generation status is indicated. Depending on the application
state, various security levels (such as protected and unprotected mode) are supported
by the security level control state machine.
Watchdog Timer (WDT)
The Watchdog Timer is one of the fail-safe mechanisms that have been implemented to
prevent the controller from malfunctioning. However, the Watchdog Timer can detect
only long term malfunctions.
1.2.9 Clock Generation Unit (CGU)
The C166S V2 Clock Generation Unit uses either an oscillator or crystal to generate the
system clock. A programmable on-chip PLL adds high flexibility to clock generation for
the C166S V2.
1.2.10 On-Chip Bootstrap Loader
As in the C166, the on-chip bootstrap loader allows the start code to be moved into
internal RAM via the serial interface.