Infineon Technologies C166S V2, User Manual

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User Manual
C166S V2
C166S V2 Memory Organization
User Manual 3-100 V 1.7, 2001-01
time data is pushed on the system stack, and incremented after each time the data is
pulled from the system stack. Only word accesses are supported to the system stack.
The 24 bit stack pointer points to the address of the latest system stack entry, rather than
to the next available system stack address.
A stack overflow (STKOV) register and a Stack Underflow (STKUN) register are
provided to control the lower and upper limits of the selected stack area. These two stack
boundary registers can be used for protection against data destruction.
3.6.1 Data Organization in Global General Purpose Registers
The C166S V2 CPU differentiates between global memory mapped General Purpose
Register (GPR) banks and local not mapped GPR banks. In addition to the memory
mapped register banks, the C166S V2 CPU has two local not memory mapped GPR
register banks for very fast context switching (see
Section 2.4 ).
Note: The local GPR banks are not memory mapped and the GPRs cannot be accessed
using a long or indirect memory address.
The C166S V2 CPU supports register bank (context) switching. Multiple global memory
mapped register banks can physically exist within the DPRAM at the same time;
however, only the global register bank selected by the Context Pointer register (CP) is
active at a given time. Selecting a new active global register bank is done by simply
updating the CP register.