Infineon Technologies C166S V2, User Manual

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User Manual
C166S V2
Instruction Pipeline
User Manual 4-103 V 1.7, 2001-01
4 Instruction Pipeline
The pipeline of the C166S V2 CPU has seven stages. Each stage processes its
individual task. The first two stages form the instruction fetch pipeline and the remaining
five stages constitute the instruction processing pipeline. The instruction fetch pipeline is
used to pre-fetch instructions and to store them into an instruction FIFO. The
preprocessing of branch instructions in combination with the instruction FIFO allows
filling of the execution pipeline with a continuous flow of instructions. In the case of an
incorrectly predicted instruction flow, the instruction fetch pipeline is bypassed to reduce
the number of dead cycles. All instructions must pass through each of the five stages of
the instruction processing pipeline regardless of the need of some stages to complete
an execution of certain instructions. The following illustrates the pipeline stages
operation.
1st -> PREFETCH:
This stage pre-fetches instructions from the PMU in the predicted order. The instructions
are pre-processed in the branch detection unit to detect branches. The prediction logic
decides if the branches are assumed to be taken or not.
2st -> FETCH:
The instruction pointer of the next instruction to be fetched is calculated according to the
branch prediction rules. For zero-cycle branch execution, the Branch Folding Unit pre-
processes and combines detected branches with the preceding instructions. Pre-fetched
instructions are stored in the instruction FIFO. At the same time, instructions are
transported out of the instruction FIFO to be executed in the instruction processing
pipeline.
3st -> DECODE:
The instructions are decoded and, if required, the register file is accessed to read the
GPR used in indirect addressing modes.
4st -> ADDRESS:
All the operand addresses are calculated. The SP register is de/incremented for all
instructions which implicitly access the system stack.
5st -> MEMORY:
All the required operands are fetched.
6st -> EXECUTE:
An ALU or MAC-Unit operation is performed on the previously fetched operands. The
Condition flags are updated. All explicit write operations to CPU-SFR registers and all
auto-in/decrement operations of GPRs used as indirect address pointers are performed.
7st -> WRITE BACK: