Infineon Technologies C166S V2, User Manual

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User Manual
C166S V2
Central Processing Unit
User Manual 2-49 V 1.7, 2001-01
2.5.2.1 Addressing via Data Page Pointer DPP
The four non-bit addressable Data Page Pointer registers select up to four different data
pages. The lower 10 bits of each DPP register select one of the 1024 possible 16-
Kilobyte data pages while the upper 6 bits are reserved for the future use. The DPP
registers provide an access to the entire memory space in 16 Kilobytes pages.
The DPP registers are implicitly used whenever data accesses to any memory location
are made via indirect or direct long 16-bit addressing modes (except for override
accesses via EXTended instructions and PEC data transfers).
Data paging is performed by concatenating the lower 14-bits of an indirect or direct long
16-bit address with the contents of the DDP register selected by the upper two bits of the
16-bit address. The contents of the selected DPP register specifies one of the 1024
possible data pages. This data page base address together with the 14-bit page offset
forms the physical 24-bit address.
Figure 2-15 Data Page Pointer Addressing
After reset, the DPP registers select data pages 3...0 within segment 0. If the user does
not want to use any data paging, no further action is required.
0 9
DPP
0 15 14
16-Bit Data Address
0 23 15 14
00’0000
H
01’0000
H
FE’0000
H
FF’0000
H
Memory
DPP3 - 11
DPP2 - 10
DPP1 - 01
DPP0 - 00
selects DPP
Segment Segment offset
Page
Page offset
0
254
x
255
1