Infineon Technologies C166S V2, User Manual

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User Manual
C166S V2
Central Processing Unit
User Manual 2-46 V 1.7, 2001-01
2.5.1 Short Addressing Modes
All of these addressing modes use an implicit base offset address to specify a 24-bit
physical address.
Short addressing modes allow access to the GPR, SFR or bit addressable memory
space:
Physical Address = Base A
∆
*
Short Address
Note:
∆
is 1 for byte GPRs,
∆
is 2 for word GPRs..
Rw, Rb: Specifies direct access to any GPR in the currently active context (global reg-
ister bank or local register bank). Both ’Rw’ and ’Rb’ require four bits in the
instruction format.The base address of the global register bank is determined
by the contents of register CP. ’Rw’ specifies a 4-bit word GPR address relative
to the base address (CP), while ’Rb’ specifies a 4-bit byte GPR address rela-
tive to the base address (CP). In case of an active local register bank this 4
bits are used directly to address the GPR.
reg: Specifies direct access to any (E)SFR or GPR in the currently active context
(global or local register bank). The ’reg’ value requires eight bits in the instruc-
tion format. Short ’reg’ addresses in the range from 00
H
to EF
H
always specify
(E)SFRs. In that case, the factor ’D’ equates 2 and the base address is
00’FE00
H
for the standard SFR area or 00’F000
H
for the extended ESFR
area. The ‘reg’ accesses to the ESFR area require a preceding EXT*R instruc-
tion to switch the base address. Depending on the opcode, either the total
word (for word operations) or the low byte (for byte operations) of an SFR can
Table 2-5 Short addressing modes
Mnemonic Physical Address Short Address
Range Scope of Access
Rw (CP) + 2*Rw or local Rw = 0...15 GPRs(Word)
Rb (CP) + 1*Rb or local Rb = 0...15 GPRs(Byte)
reg 00’FE00
H
+ 2*reg
00’F000
H
+ 2*reg
(CP)+2*(reg
∧
0F
H
) or local
(CP)+1*(reg
∧
0F
H
) or local
reg = 00
H
...EF
H
reg = 00
H
...EF
H
reg = F0
H
...FF
H
reg = F0
H
...FF
H
SFRs (Word, Low byte)
ESFRs(Word, Low byte)
GPRs(Word)
GPRs(Bytes)
bitoff 00’FD00
H
+ 2*bitoff
00’FF00
H
+ 2*(bitoff
∧
7F
H
)
00’F100
H
+ 2*(bitoff
∧
7F
H
)
(CP) + 2*(bitoff
∧
0F
H
) or
local
bitoff = 00
H
...7F
H
bitoff = 80
H
...EF
H
bitoff = 80
H
...EF
H
bitoff = F0
H
...FF
H
RAM Bit word offset
SFR Bit word offset
ESFR Bit word offset
GPR Bit word offset
bitaddr Word offset as with bitoff.
Immediate bit position. bitoff = 00
H
...FF
H
bitpos= 0...15
Any single bit