HP 70340A, User Manual

Page: 345 / 445

Bit Description
0 A one in this bit p osition indicates that the YIG oscillator calibration is curren tly
b eing run.
1 A one in this bit p osition indicates that the Signal Generator hardw are is settling (for
example, the p o w er lev el is c hanging).
2 - 6 These bits are alwa ys set to 0.
7 A one in this bit p osition indicates that the Signal Generator lev el correct routine is
b eing run.
8 - 15 These bits are alwa ys set to 0.
The Questionable Data Status Group
The Questionable Data status group is used to determine the sp ecic condition that set
bit 3 in the Status Byte. The Questionable Data status group consists of the Questionable
Condition register, Questionable Negative T ransition register, Questionable P ositiv e T ransition
register, Questionable Ev en t register, and Questionable Ev en t Enable register. The bits in the
Questionable Ev en t register pro vide y ou with the follo wing information:
Bit Description
0 - 2 These bits are alwa ys set to 0.
3 A one in this bit p osition indicates that the RF output p o w er might b e uncalibrated
or unlev eled.
4 A one in this bit p osition indicates that the in ternal frequency reference o v en is cold
(option 1E5 only).
5 A one in this bit p osition indicates that the Signal Generator output frequency might
b e uncalibrated. This bit is set if the signal is out of lo c k, uncalibrated, or the o v en is
cold.
6 This bit is alwa ys set to 0.
7 A one in this bit p osition indicates that one or more of the mo dulations might b e
uncalibrated.
8 This bit is set to 1 whenev er bits 3, 5, or 7 in this register are set to 1. This bit is set
if frequency p o w er or mo dulation is uncalibrated.
9 - 15 These bits are alwa ys set to 0.
Status Register System Programming Example
In the follo wing example, the Status Register System is programmed to set bit 6 of the status
b yte (the SR Q bit) high after the Signal Generator hardw are has settled. Bit 6 is monitored
and, once it is set high, the con troller prin ts \ HARDWARE IS SETTLED " on its screen.
10 OUTPUT 719;"STAT:OPER:PTR 0" Disable al l bits in the Op er ation Positive T r ansi-
tion r e gister.
20 OUTPUT 719;"STAT:OPER:NTR 2" Enable bit 2 (the \har dwar e settling" bit) in the
Op er ation Ne gative T r ansition r e gister.
30 OUTPUT 719;"STAT:OPER:ENAB 2" Enable bit 2 (the \har dwar e settling" bit) in the
Op er ation Event Enable r e gister.
Programming Commands 7-121
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