Fujitsu F2 MC-8FX Family, Hardware Manual

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CHAPTER 8 INTERRUPTS
8.1.1 Interrupt Level Setting Registers (ILR0 to ILR5)
The interrupt level setting registers (ILR0 to ILR5) contain 24 pairs of bits assigned for
the interrupt requests from different peripheral resources. Each pair of bits (interrupt
level setting bits as two-bit data) sets each interrupt level.
■
Configuration of Interrupt Level Setting Registers (ILR0 to ILR5)
Figure 8.1-1 Configuration of Interrupt Level Setting Registers
The interrupt level setting registers assign each pair of bits for a different interrupt request. The values of
interrupt level setting bits in these registers specify interrupt service priorities (interrupt levels 0 to 3).
The interrupt level setting bits are compared with the interrupt level bits in the condition code register
(CCR: IL1, IL0).
When interrupt level 3 is set for an interrupt request, the CPU ignores the interrupt request.
Table 8.1-2 shows the relationships between interrupt level setting bits and interrupt levels.
XX:0 to 23 Corresponding interrupt number
During execution of a main program, usually, the interrupt level bits in the condition code register (CCR:
IL1, IL0) contain "11
B
".
Register Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value
ILR0 00079
H
L03 [1:0] L02 [1:0] L01 [1:0] L00 [1:0] R/W 11111111
B
ILR1 0007A
H
L07 [1:0] L06 [1:0] L05 [1:0] L04 [1:0] R/W 11111111
B
ILR2 0007B
H
L11 [1:0] L10 [1:0] L09 [1:0] L08 [1:0] R/W 11111111
B
ILR3 0007C
H
L15 [1:0] L14 [1:0] L13 [1:0] L12 [1:0] R/W 11111111
B
ILR4 0007D
H
L19 [1:0] L18 [1:0] L17 [1:0] L16 [1:0] R/W 11111111
B
ILR5 0007E
H
L23 [1:0] L22 [1:0] L21 [1:0] L20 [1:0] R/W 11111111
B
Table 8.1-2 Relationships Between Interrupt Level Setting Bits and Interrupt Levels
LXX LXX
Requested Interrupt
Level
Priority
0 0 0 Highest
0 1 1
1 0 2
1 1 3 Lowest (No interrupt accepted)