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CHAPTER 28 256-KBIT FLASH MEMORY

28.5.1

Data Polling Flag (DQ7)

The data polling flag (DQ7) is a hardware sequence flag used to indicate that the
automatic algorithm is being executing or has been completed using the data polling
function.

■

Data Polling Flag (DQ7)

Table 28.5-3 and Table 28.5-4 show the state transition of the data polling flag.

●

At programming

When read access takes place during execution of the automatic write algorithm, the flash memory outputs

the inverted value of bit 7 in the last data written to DQ7.

If read access takes place on completion of the automatic write algorithm, the flash memory outputs bit 7 of

the value read from the read-accessed address to DQ7.

●

At chip erasing

When read access is made to the sector currently being erased during execution of the chip erase algorithm,

bit 7 of flash memory outputs "0". Bit 7 of flash memory outputs "1" upon completion of chip erasing.

Note:

Once the automatic algorithm has been started, read access to the specified address is ignored.
Data reading is allowed after the data polling flag (DQ7) is set to "1". Data reading after the end of
the automatic algorithm should be performed following read access made to confirm the completion
of data polling.

Table 28.5-3 State Transition of Data Polling Flag (During Normal Operation)

Operating state

Programming

→

Programming completed

Chip erasing

→

Erasing completed

DQ7

DQ7

→

DATA: 7

01

Table 28.5-4 State Transition of Data Polling Flag (During Abnormal Operation)

Operating state

Programming

Chip erasing

DQ7

DQ7

0

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Summary of Contents for F2 MC-8FX Family

Page 1: ...FUJITSU SEMICONDUCTOR CONTROLLER MANUAL F2MC 8FX 8 BIT MICROCONTROLLER MB95170J Series HARDWARE MANUAL Version 1 0 ...

Page 2: ......

Page 3: ...e following support page URL http www fujitsu com global services microelectronics product micom support index html Check Sheet lists the minimal requirement items to be checked to prevent problems beforehand in system development Be sure to refer to the Check Sheet for the latest cautions on development ...

Page 4: ......

Page 5: ...al Note F2MC is the abbreviation of FUJITSU Flexible Microcontroller License Purchase of Fujitsu I2 C components conveys a license under the Philips I2 C Patent Rights to use these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips Sample Programs Fujitsu provides sample programs free of charge to operate the peripheral resources o...

Page 6: ...ned herein The products described in this document are designed developed and manufactured as contemplated for general use including without limitation ordinary industrial use general office use personal use and household use but are not designed developed and manufactured as contemplated 1 for use accompanying fatal risks or dangers that unless extremely high safety is secured could have a seriou...

Page 7: ... CPU 31 5 1 Dedicated Registers 32 5 1 1 Register Bank Pointer RP 34 5 1 2 Direct Bank Pointer DP 35 5 1 3 Condition Code Register CCR 37 5 2 General purpose Registers 39 5 3 Placement of 16 bit Data in Memory 41 CHAPTER 6 CLOCK CONTROLLER 43 6 1 Overview of Clock Controller 44 6 2 Oscillation Stabilization Wait Time 50 6 3 System Clock Control Register SYCC 52 6 4 PLL Control Register PLLC 54 6 5...

Page 8: ...rupt Processing Stack Area 100 CHAPTER 9 I O PORT 101 9 1 Overview of I O Ports 102 9 2 Port 0 104 9 2 1 Port 0 Registers 106 9 2 2 Operations of Port 0 107 9 3 Port 1 109 9 3 1 Port 1 Registers 112 9 3 2 Operations of Port 1 113 9 4 Port 4 115 9 4 1 Port 4 Registers 117 9 4 2 Operations of Port 4 118 9 5 Port 5 120 9 5 1 Port 5 Registers 122 9 5 2 Operations of Port 5 123 9 6 Port 6 125 9 6 1 Por...

Page 9: ...81 12 1 Overview of Hardware Watchdog Timer 182 12 2 Configuration of Hardware Watchdog Timer 183 12 3 Registers of the Hardware Watchdog Timer 185 12 3 1 Hardware Watchdog Timer Control Register HWDC 186 12 4 Explanation of Hardware Watchdog Timer Operations and Setup Procedure Example 188 12 5 Precautions when Using Hardware Watchdog Timer 190 CHAPTER 13 WATCH PRESCALER 191 13 1 Overview of Watc...

Page 10: ...8 16 bit Composite Timer 00 01 Timer Mode Control Register TMCR0 248 16 5 4 8 16 bit Composite Timer 00 01 Data Register T00DR T01DR 251 16 6 Interrupts of 8 16 bit Composite Timer 254 16 7 Operating Description of Interval Timer Function One shot Mode 256 16 8 Operating Description of Interval Timer Function Continuous Mode 258 16 9 Operating Description of Interval Timer Function Free run Mode 2...

Page 11: ...uit 321 19 4 1 Interrupt Pin Selection Circuit Control Register WICR 322 19 5 Operating Description of Interrupt Pin Selection Circuit 325 19 6 Precautions when Using Interrupt Pin Selection Circuit 326 CHAPTER 20 UART SIO 327 20 1 Overview of UART SIO 328 20 2 Configuration of UART SIO 329 20 3 Channels of UART SIO 331 20 4 Pins of UART SIO 332 20 5 Registers of UART SIO 333 20 5 1 UART SIO Seria...

Page 12: ...ter 412 23 2 Configuration of 10 bit A D Converter 413 23 3 Pins of 10 bit A D Converter 415 23 4 Registers of 10 bit A D Converter 417 23 4 1 A D Control Register 1 ADC1 418 23 4 2 A D Control Register 2 ADC2 420 23 4 3 A D Data Registers ADDH ADDL 422 23 5 Interrupts of 10 bit A D Converter 423 23 6 Operations of 10 bit A D Converter and Its Setup Procedure Examples 424 23 7 Notes on Use of 10 b...

Page 13: ... TIME CLOCK 481 27 1 Overview of Real time clock 482 27 2 Configuration of Real Time Clock 483 27 3 Registers of Real Time Clock 487 27 3 1 Real Time Clock Control Register Upper RTCCRH 489 27 3 2 Real Time Clock Control Register Lower RTCCRL 494 27 3 3 Minute Compare Register MICR 496 27 3 4 Hour Compare Register HRCR 497 27 3 5 Day Compare Register DYCR 498 27 3 6 Month Compare Register MOCR 499...

Page 14: ... Data into Flash Memory 536 28 6 3 Erasing All Data from Flash Memory Chip Erase 538 28 7 Features of Flash Security 539 CHAPTER 29 EXAMPLE OF SERIAL PROGRAMMING CONNECTION 541 29 1 Basic Configuration of MB95170J Serial Programming Connection 542 29 2 Example of Serial Programming Connection 545 29 3 Example of Minimum Connection to Flash Microcomputer Programmer 547 APPENDIX 551 APPENDIX A I O M...

Page 15: ...ation of the MB95170J series 1 1 Feature of MB95170J Series 1 2 Product Lineup of MB95170J Series 1 3 Difference Among Products and Notes on Selecting Products 1 4 Block Diagram of MB95170J Series 1 5 Pin Assignment 1 6 Package Dimension 1 7 Pin Description 1 8 I O Circuit Type ...

Page 16: ...on Bit operation instructions etc Clock Main clock Main PLL clock Subclock Timer 8 16 bit compound timer x 2 channels 16 bit PPG x 8 channels Timebase timer Watch prescaler UART SIO With full duplex double buffer An asynchronous UART clock or a synchronous SIO serial data transfer capable I2 C Built in wake up function External interrupt Interrupt by the edge detection Select rising edge falling e...

Page 17: ...eral purpose I O ports N ch open drain 2 General purpose I O ports CMOS 52 Programmable input voltage levels of port Automotive input level CMOS input level Hysteresis input level Flash memory security function Protects the content of Flash memory Flash memory device only Purchase of Fujitsu I2 C components conveys a license under the Philips I2 C Patent Rights to use these components in an I2C sy...

Page 18: ...nd peripheral functions Product Lineup of MB95170J Series Table 1 2 1 Product Lineup of MB95170J Series Part Number Parameter MB95F176JS MB95F176JW Type Flash memory product Flash memory product ROM capacity 32K MAX 32K MAX RAM capacity 1K MAX 1K MAX Reset output No No Option Clock system Single Clock Dual Clock Low voltage detection reset Yes Yes Clock supervisor Yes Yes ...

Page 19: ...t in full duplex double buffer Changeable data length 5 6 7 8 bit Built in baud rate generator NRZ method transfer format Error detected function LSB first or MSB first can be selected Serial data transfer is available for clock synchronous SIO and clock asynchronous UART 10 bit A D converter 8 channels 10 bit resolution can be selected LCD controller LCDC MAX 28 SEG x 4 COM Blinking function 2 8 ...

Page 20: ...mming Embedded AlgorithmTM 1 Write Erase Erase Suspend Resume commands A flag indicating completion of the algorithm Number of write earse cycles Minimum 10000 times Data retention time 20 years Block protection with external programming voltage Flash Security Feature for protecting the content of the Flash Standby Mode Sleep stop watch 3 and timebase timer Table 1 2 2 CPU and Peripheral Function ...

Page 21: ...e different to the values on the flash memory and mask ROM products do not use these values in the program The Evaluation product do not support the functions of some bits in single byte registers Read write access to these bits does not cause hardware malfunctions The Evaluation and Flash memory product are designed to behave completely the same way in terms of hardware and software Difference of...

Page 22: ...8 CHAPTER 1 DESCRIPTION Package and Its Corresponding Product usable unusable MB95F176JS MB95F176JW FPT 64P M23 FPT 64P M24 Package Product ...

Page 23: ... P64 EC1 SEG20 P65 SEG21 RST X0 X1 P95 X1A P94 X0A MOD VCC VSS C DVcc DVss x 2 P11 UO0 TO01 P12 UCK0 TO00 I 2 C F 2 MC 8FX CPU UART SIO 10 bit A D converter C LCDC 16 bit PPG 0 RTC ROM RAM Port Port External interrupt ch8 to ch11 Interrupt control Wild register Reset control Clock control Watch prescaler Watch counter External interrupt ch0 to ch7 Internal bus Other pins It is general purpose port...

Page 24: ...PC7 SEG15 TRG7 PC6 SEG14 TRG6 PC5 SEG13 TRG5 PC4 SEG12 TRG4 PC3 SEG11 TRG3 PC2 SEG10 TRG2 PC1 SEG09 TRG1 PC0 SEG08 TRG0 PB7 SEG07 PB6 SEG06 PB5 SEG05 Vcc PB4 SEG04 PB3 SEG03 PB2 SEG02 PB1 SEG01 PB0 SEG00 TPCLK CALPL PA3 COM3 P50 SCL0 RST P94 X0A P95 X1A C 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P51 SDA0 PA0 COM0 PA1 COM1 PA2 COM2 P13 ADTG PPG0 P65 SEG21 PE4 SEG28 INT1 PE5 SEG29 INT1 PE6 SE...

Page 25: ...Code Reference P LFQFP64 12 12 0 65 64 pin plastic LQFP FPT 64P M23 FPT 64P M23 C 2003 FUJITSU LIMITED F64034S c 1 1 0 65 026 0 10 004 1 16 17 32 49 64 33 48 12 00 0 10 472 004 SQ 14 00 0 20 551 008 SQ INDEX 0 32 0 05 013 002 M 0 13 005 0 145 0 055 0057 0022 A 059 004 008 0 10 0 20 1 50 0 8 0 25 010 Mounting height 0 50 0 20 020 008 0 60 0 15 024 006 0 10 0 10 004 004 Details of A part Stand off D...

Page 26: ...0 64 pin plastic LQFP FPT 64P M24 FPT 64P M24 LEAD No Details of A part 0 25 010 Stand off 004 004 0 10 0 10 024 006 0 60 0 15 020 008 0 50 0 20 1 50 0 20 0 10 008 004 059 0 8 A 0 08 003 006 002 0 145 0 055 0 08 003 M 008 002 0 20 0 05 0 50 020 12 00 0 20 472 008 SQ 10 00 0 10 394 004 SQ INDEX 49 64 33 48 17 32 16 1 2005 FUJITSU LIMITED F64036S c 1 1 C Mounting height Dimensions in mm inches Note ...

Page 27: ...h 0 data output 4 P10 UI0 EC0 G General purpose I O port The pin is shared with 8 16 bit compound timer ch 0 clock input and UART SIO ch 0 data input 5 P07 S23 INT07 AN07 S General purpose I O port The pins are shared with LCDC SEG output SEG23 external interrupt input and A D converter analog input 6 P06 S22 INT06 AN06 General purpose I O port The pins are shared with LCDC SEG output SEG22 extern...

Page 28: ...5 PA1 COM1 26 PA2 COM2 27 PA3 COM3 28 PB0 S00 TP CLK CALPL M General purpose I O port The pins are shared with LCDC SEG output and RTC I O 29 PB1 S01 M General purpose I O port The pins are shared with LCDC SEG output 30 PB2 S02 31 PB3 S03 32 PB4 S04 33 PB5 S05 34 PB6 S06 35 PB7 S07 36 PC0 S08 TRG0 General purpose I O port The pins are shared with LCDC SEG output and PPG trigger input 37 PC1 S09 T...

Page 29: ...LCDC drive 55 DVSS Power supply pin GND 56 P91 V2 PPG7 R General purpose I O port The pins are shared with power supply pins for LCDC drive and 16 bit PPG 7 output 57 P92 V1 PPG6 General purpose I O port The pins are shared with power supply pins for LCDC drive and 16 bit PPG 6 output 58 P43 PPG5 H General purpose I O port The pins are shared with and 16 bit PPG 5 output 59 P42 PPG4 H General purp...

Page 30: ...16 CHAPTER 1 DESCRIPTION 1 FPT 64P M23 FPT 64P M24 2 For the I O circuit type refer to 1 8 I O Circuit Type ...

Page 31: ... speed side Feedback resistance appro x 10 MΩ B Only for input Hysteresis input B Hysteresis input G CMOS output CMOS input Hysteresis input With pull up control Automotive input H CMOS output Hysteresis input With pull up control Automotive input X0 X0A X1 X1A N ch Standby control Clock input Mode input Reset input R P ch N ch P ch Pull up control Standby control Digital output Digital output Hys...

Page 32: ... input Table 1 8 1 I O Circuit Type 2 3 Type Circuit Remarks P ch N ch Standby con Digital output Digital output Hysteresis input Automotive input N ch Standby control Digital output CMOS input Hysteresis input Automotive input R P ch P ch N ch Pull up control A D control Standby control Analog input Digital output Hysteresis input Digital output Automotive input P ch N ch Standby control Hysteres...

Page 33: ... Remarks P ch N ch LCD control Digital output Hysteresis input CMOS input Digital output Standby control LCD output Automotive input P ch N ch Standby control Digital output Hysteresis input LCD control Digital output External interrupt control LCD output Automotive input P ch N ch LCD control Standby control LCD built in division resistance I O Hysteresis input Digital output Digital output Autom...

Page 34: ...20 CHAPTER 1 DESCRIPTION ...

Page 35: ...21 CHAPTER 2 HANDLING DEVICES This chapter gives notes on using 2 1 Device Handling Precautions ...

Page 36: ...pply current increases rapidly and might thermally damage elements Stable Supply Voltage Supply voltage should be stabilized A sudden change in power supply voltage may cause a malfunction even within the guaranteed operating range of the Vcc power supply voltage For stabilization in principle keep the variation in Vcc ripple p p value in a commercial frequency range 50 60 Hz not to exceed 10 of t...

Page 37: ...agnetic emission level to prevent abnormal operation of strobe signals caused by the rise in the ground level and to conform to the total output current rating Moreover connect the current supply source with the VCC and VSS pins of this device at the low impedance It is also advisable to connect a ceramic bypass capacitor of approximately 0 1 μF between VCC and VSS pins near this device Mode Pin M...

Page 38: ...24 CHAPTER 2 HANDLING DEVICES ...

Page 39: ...25 CHAPTER 3 MEMORY SPACE This chapter describes memory space 3 1 Memory Space 3 2 Memory Map ...

Page 40: ... area contains the control registers and data registers for on chip peripheral resources As the extended I O area is allocated as part of memory space it can be accessed in the same way as for memory Data area Static RAM is incorporated as the internal data area The internal RAM capacity is different depending on the product The RAM area from 80H to FFH can be accessed at higher speed by using dir...

Page 41: ...tions For details see Section 5 1 1 Register Bank Pointer RP and Section 5 2 General purpose Registers Vector Table Area Addresses FFC0H to FFFFH This area is used as the vector table for vector call instructions CALLV interrupts and resets The vector table area is allocated at the top of the ROM area At the individual addresses in the vector table the start addresses of their respective service r...

Page 42: ...080H 0100H Data area Register banks General purpose register area Extended direct addressing area 0200H Address 1 Access prohibited 0F00H Extended I O area Address 2 Program area FFC0H FFFFH Vector table area Product Flash memory RAM Address 1 Address 2 MB95F176JS MB95F176JW 32K bytes 1K byte 0480H 08000H ...

Page 43: ...29 CHAPTER 4 MEMORY ACCESS MODE This chapter describes the memory access mode 4 1 Memory Access Mode ...

Page 44: ...ss is fixed as FFFDH The value of FFFCH can be any value Be sure to set the mode data of internal ROM to 00H to select single chip mode Figure 4 1 1 Mode Data Settings After a reset the CPU fetches mode data first The CPU then fetches the reset vector after the mode data The instruction is performed from the address set by reset vector Mode pin MOD Be sure to set the mode pin MOD to VSS Address bi...

Page 45: ...31 CHAPTER 5 CPU This chapter describes functions and operations of the CPU 5 1 Dedicated Registers 5 2 General purpose Registers 5 3 Placement of 16 bit Data in Memory ...

Page 46: ...alue set immediately after a reset is the mode data read address FFFDH Accumulator A The accumulator is a 16 bit register for arithmetic operation It is used for a variety of arithmetic and transfer operations of data in memory or data in other registers such as the temporary accumulator T The data in the accumulator can be handled either as word 16 bit data or byte 8 bit data For byte length arit...

Page 47: ...ess The initial value after a reset is 0000H Stack pointer SP The stack pointer is a 16 bit register which holds the address referenced when an interrupt or subroutine call occurs and by the stack push and pop instructions During program execution the value of the stack pointer indicates the address of the most recent data pushed onto the stack The initial value after a reset is 0000H Program stat...

Page 48: ...specified by setting a value between 0 and 31 in the upper five bits of the register bank pointer Each register bank has eight 8 bit general purpose registers which are selected by the lower three bits of the op code The register bank pointer allows the space from 0100H to up to 01FFH to be used as a general purpose register area Note however that the available area is limited depending on the pro...

Page 49: ...s specified with the value in the value of the direct bank pointer and the operand Table 5 1 1 shows the relationship between direct bank pointer DP and access area Table 5 1 2 lists the direct addressing instructions RP DP CCR bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 PS R4 R3 R2 R1 R0 DP2 DP1 DP0 H I IL1 IL0 N Z V C 000B DP Initial value Table 5 1 1 Di...

Page 50: ...ct Address Instruction List Applicable Instruction CLRB dir bit SETB dir bit BBC dir bit rel BBS dir bit rel MOV A dir CMP A dir ADDC A dir SUBC A dir MOV dir A XOR A dir AND A dir OR A dir MOV dir imm CMP dir imm MOVW A dir MOVW dir A ...

Page 51: ...e the flag is set to 0 Do not use this flag for any operation other than addition and subtraction as the flag is intended for decimal adjusted instructions Negative flag N This flag is set to 1 when the value of the most significant bit is 1 as the result of an operation and set to 0 if the value is 0 Zero flag Z This flag is set to 1 when the result of an operation is 0 and set to 0 otherwise Ove...

Page 52: ...nd 0 respectively Interrupt level bits IL1 IL0 These bits indicate the level of the interrupt currently accepted by the CPU The interrupt level is compared with the value of the interrupt level setting register ILR0 to ILR5 that corresponds to the interrupt request IRQ0 to IRQ23 of each peripheral resource The CPU services an interrupt request only when its interrupt level is smaller than the valu...

Page 53: ...ister area in RAM Up to 32 banks can be used where each bank consists of eight registers R0 to R7 The register bank pointer RP specifies the register bank currently being used and the lower three bits of the op code specify general purpose register 0 R0 to 7 R7 Figure 5 2 1 shows the configuration of the register banks Figure 5 2 1 Configuration of Register Banks For information on the general pur...

Page 54: ...fying a dedicated register bank at the beginning of an interrupt service routine automatically saves the general purpose registers before the interrupt This eliminates the need for pushing general purpose register data onto the stack allowing the CPU to accept interrupts at high speed Notes When coding an interrupt service routine be careful not to change the value of the interrupt level bits CCR ...

Page 55: ... bit data In the same way even when the operands in an instruction specifies 16 bit data the upper byte is stored at the address closer to the op code instruction and the lower byte is stored at the next address That is true whether the operands are either memory addresses or 16 bit immediate data Figure 5 3 2 shows how 16 bit data in an instruction is placed Figure 5 3 2 Storing 16 bit Data in In...

Page 56: ...42 CHAPTER 5 CPU ...

Page 57: ... Clock Control Register SYCC 6 4 PLL Control Register PLLC 6 5 Oscillation Stabilization Wait Time Setting Register WATR 6 6 Standby Control Register STBC 6 7 Clock Modes 6 8 Operations in Low power Consumption Modes Standby Modes 6 9 Clock Oscillator Circuits 6 10 Overview of Prescaler 6 11 Configuration of Prescaler 6 12 Operating Explanation of Prescaler 6 13 Notes on Use of Prescaler ...

Page 58: ...der circuits The clock controller controls the internal clock according to the clock mode standby mode settings and the reset operation The current clock mode selects the internal operating clock and the standby mode selects whether to enable or disable clock oscillation and signal supply The clock controller selects the optimum power consumption and features depending on the combination of clock ...

Page 59: ...SYCC Oscillation stabilization wait circuit Supply to CPU Supply to peripheral resources Sleep signal Stop signal Watch or timebase timer Clock for timebase timer Main clock control Oscillation stabilization wait time setting register WATR Source clock selection control circuit MPMC1 PLL controller register PLLC 1 2 4 3 5 6 7 1 Main clock FCH 2 Subclock FCL 3 Mainclock 4 Subclock 5 Main PLL clock ...

Page 60: ...wait circuit This block outputs the oscillation stabilization wait time signal for each clock from 14 types of main clock oscillation stabilization signals created by the timebase timer and 15 types of subclock oscillation stabilization signals created by the watch prescaler System clock control register SYCC This register is used to control current clock mode display clock mode selection machine ...

Page 61: ...ct the timebase timer or watch prescaler output as a count clock Check the description of each peripheral resource for details Table 6 1 1 Clock Modes and Machine Clock Selection Clock Mode Machine Clock Main clock mode The machine clock is generated from the main clock main clock divided by 2 Main PLL clock mode The machine clock is generated from the main PLL clock main clock multiplied by the P...

Page 62: ...aler and watch counter while stopping clock supply to other circuits As a result all the functions other than the timebase timer watch prescaler watch counter external interrupt and low voltage detection reset are stopped Timebase timer mode is only the standby mode for main clock mode or main PLL clock mode Watch mode Two system clock product only Stops main clock oscillation but supplies clock s...

Page 63: ...ed Operating Stopped Operating Stopped Stopped Stopped Main PLL clock Stopped 1 Operat ing Stopped Stopped 1 Operat ing Stopped Stopped 1 Stopped Stopped Stopped Subclock Operating 2 Operating Operating 2 Operating Operating 2 Operating Operat ing 2 Stopped CPU Operating Operating Stopped Stopped Stopped Stopped Stopped Stopped ROM Operating Operating Value held Value held Value held Value held Va...

Page 64: ...ait time is counted by using the timebase timer The subclock oscillation stabilization wait time is counted by using the watch prescaler The count can be set in the oscillation stabilization wait time setting register WATR Set it in keeping with the oscillator characteristics When a power on reset occurs the oscillation stabilization wait time is fixed to the initial value Table 6 2 1 shows the le...

Page 65: ...tion The clock controller automatically waits for the oscillation stabilization wait time to elapse as needed when the operating state causes a transition Depending on the state transition however the clock controller does not always wait for the oscillation stabilization wait time For details on state transitions see 6 7 Clock Modes and 6 8 Operations in Low power Consumption Modes Standby Modes ...

Page 66: ...k oscillation 1 Stops subclock oscillation SRDY Subclock oscillation stability bit 0 Indicates the subclock oscillation stabilization wait state or subclock oscillation being stopped 1 Indicates subclock oscillation being stable Cock mode selection bits 0 0 Subclock mode 0 1 1 0 Main clock mode 1 1 Main PLL clock mode Clock mode monitor bits 0 0 Subclock mode 0 1 Meaningless 1 0 Main clock mode 1 ...

Page 67: ... SRDY bit indicates that the oscillation stabilization wait time for the subclock has passed When set to 0 the SRDY bit indicates that the clock controller is in the subclock oscillation stabilization wait state or that subclock oscillation has been stopped This bit is read only any value attempted to be written is meaningless On single system clock product the value of the bit is meaningless bit2...

Page 68: ...ndicates main PLL clock oscillation being stable MPMC1 Main PLL clock multiplier setting bits 0 0 Main clock x 1 0 1 Main clock x 2 1 0 Main clock x 2 5 1 1 Setting prohibited MPEN Main PLL clock oscillation enable bit 0 Disables main PLL clock oscillation 1 Enables main PLL clock oscillation bit7 Address 0006H MPMC1 Initial value 00000000B MPEN MPMC0 R W R0 W0 R0 W0 R0 W0 R W R W R0 W0 R W R W Re...

Page 69: ...MPEN is set to 1 or with the clock mode selection bits in the system clock control register SYCC SCS1 0 are set to 11 It is however possible to set these bits at the same time as setting MPEN to 1 bit4 MPRDY Main PLL clock oscillation stability bit Indicates whether main PLL clock oscillation has become stable When set to 1 the MPRDY bit indicates that the oscillation stabilization wait time for t...

Page 70: ...H 0 5 μs 21 2 FCH 0 0 μs 21 2 FCH 0 0 μs 21 2 FCH 0 0 μs 1 1 1 0 1 1 0 1 1 1 0 0 1 0 1 1 1 0 1 0 1 0 0 1 1 0 0 0 0 1 1 1 0 1 1 0 0 1 0 1 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 SWT3 SWT2 SWT1 SWT0 Sub Oscillation Clock FCL 32 768 kHz 1 1 1 1 1 1 1 0 1 1 0 1 1 1 0 0 1 0 1 1 1 0 1 0 1 0 0 1 1 0 0 0 0 1 1 1 0 1 1 0 0 1 0 1 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 214 2 FCL About 0 5 s 215 2 FCL About ...

Page 71: ...he system clock control register SYCC SRDY set to 1 or in subclock mode You can also update them while the subclock is stopped with the subclock oscillation stop bit in the system clock control register SYCC SUBS set to 1 in main clock mode or main PLL clock mode SWT3 SWT2 SWT1 SWT0 Number of Cycles Subclock FCL 32 768 kHz 1111 215 2 215 2 FCL About 1 0 s 1110 214 2 214 2 FCL About 0 5 s 1101 213 ...

Page 72: ...m in subclock mode Table 6 5 1 Functions of Bits in Oscillation Stabilization Wait Time Setting Register WATR 2 2 Bit name Function MWT3 MWT2 MWT1 MWT0 Number of Cycles Main clock FCH 4 MHz 1111 214 2 214 2 FCH About 4 10 ms 1110 213 2 213 2 FCH About 2 05 ms 1101 212 2 212 2 FCH About 1 02 ms 1100 211 2 211 2 FCH 511 5 μs 1011 210 2 210 2 FCH 255 5 μs 1010 29 2 29 2 FCH 127 5 μs 1001 28 2 28 2 FC...

Page 73: ...59 CHAPTER 6 CLOCK CONTROLLER ...

Page 74: ... Has no effect on the operation 1 Generates a 3 machine clock reset signal SPL Pin state setting bit 0 Holds external pins in their immediately preceding state in stop mode timebase timer mode or watch mode 1 Places external pins in a high impedance state in stop mode timebase timer mode or watch mode Sleep bit SLP Read Write 0 Always reads 0 Has no effect on the operation 1 Causes transition to s...

Page 75: ...atch mode When set to 1 the bit places external pins in a high impedance state in stop mode timebase timer mode and watch mode Those pins are pulled up for which pull up resistor connection has been selected in the pull up setting register bit4 SRST Software reset bit Sets a software reset When set to 0 the bit is meaningless When set to 1 the bit generates a 3 machine clock reset signal When read...

Page 76: ...clock mode setting bits SYCC SCS1 0 in the system clock control register If you write 1 simultaneously to two or more of the stop bit STP sleep bit SLP software reset bit SRST and watch bit TMD priority is given to them in the following order 1 Software reset bit SRST 2 Stop bit STP 3 Watch bit TMD 4 Sleep bit SLP When released from the standby mode the device returns to the normal operating statu...

Page 77: ...main clock mode is always set regardless of the clock mode used before the reset Operations in Subclock Mode on Two system Clock Product Subclock mode uses the subclock as the machine clock for the CPU and peripheral resources with main clock oscillation stopped In this mode the timebase timer remains stopped as it requires the main clock for operation If you set standby mode during operation in s...

Page 78: ...er SYCC Figure 6 7 1 Clock Mode State Transition Diagram Two system Clock Product Power on Reset state Main clock oscillation stabilization wait time Main PLL clock oscillation stabiliza tion wait time Main clock oscillation stabilization wait time Subclock oscillation stabilization wait time Subclock mode Main clock mode Main clock main PLL clock oscillation stabilization wait time 1 2 3 5 4 6 8 ...

Page 79: ...Mode State Transition Diagram Single System Clock Product Power on Reset state Main PLL clock oscillation stabiliza tion wait time Main PLL clock mode Main clock mode 5 Reset occurs in each state 1 2 3 4 Main clock oscillation stabilization wait time ...

Page 80: ...evice does not wait for the main PLL clock oscillation stabilization wait time to elapse if the main PLL clock has been oscillating according to the setting of the main PLL clock oscillation enable bit in the PLL control register PLLC MPEN 4 5 Main PLL clock Main clock The device enters main clock mode when the system clock selection bits in the system clock control register SYCC SCS1 0 are set to...

Page 81: ...sponse to an interrupt or reset Before transition to normal operation the device waits for the oscillation stabilization wait time to elapse as required When released from standby mode by a reset the device returns to main clock mode When released from standby mode by an interrupt the device enters the clock mode in which the device was before entering the standby mode Pin States in Standby Mode T...

Page 82: ...ed before Setting Standby Mode Before setting standby mode make sure that clock mode transition has been completed by comparing the values of the clock mode monitor bit SYCC SCM1 0 and clock mode setting bit SYCC SCS1 0 in the system clock control register An Interrupt Request may Suppress Transition to Standby Mode If an attempt is made to set a standby mode while an interrupt request with an int...

Page 83: ...Mode State Transition Diagram Two system Clock Product Power on Reset state Main clock oscillation stabilization wait time Normal RUN state Watch mode 2 1 Main clock main PLL clock Subclock oscillation stabilization wait time Main PLL clock oscillation stabiliza tion wait time Timebase timer mode Stop mode Sleep mode 1 2 3 4 5 6 7 8 9 Reset occurs in each state ...

Page 84: ...lock Product Power on Reset state Reset occurs in each state Main clock main PLL clock oscillation stabilization wait time Main PLL clock oscillation stabiliza tion wait time Timebase timer mode Stop mode Sleep mode 1 2 3 4 5 6 7 Main clock oscillation stabilization wait time Normal RUN state 1 2 ...

Page 85: ...o the stop bit in the standby control register STBC STP 4 In response to an external interrupt the device returns to the RUN state after waiting for the oscillation stabilization wait time required for each clock mode When the device waits for a PLL oscillation stabilization wait time it waits for the relevant oscillation stabilization wait time or PLL oscillation stabilization wait time to elapse...

Page 86: ...s while retaining the contents of registers and RAM that exist immediately before the transition to sleep mode but the peripheral resources except the watchdog timer continue operating Transition to sleep mode Writing 1 to the sleep bit in the standby control register STBC SLP causes the device to enter sleep mode Cancellation of sleep mode A reset or an interrupt from a peripheral resource releas...

Page 87: ...mebase timer interrupt request may be generated while the device is waiting for main clock oscillation to stabilize after being released from stop mode by an interrupt If the interrupt interval time of the timebase timer is shorter than the main clock oscillation stabilization wait time you should disable interrupt requests output from the timebase timer before entering stop mode thereby preventin...

Page 88: ... 0 are 10 or 11 The device can enter timebase timer mode only when the clock mode is main clock mode or main PLL clock mode Upon transition to timebase timer mode the states of external pins are retained when the pin state setting bit in the standby control register STBC SPL is 0 and the states of external pins become high impedance when that bit is 1 those pins are pulled up for which pull up res...

Page 89: ... system clock control register SYCC SCM1 0 are 00 The device can enter watch mode only when the clock mode is subclock mode Upon transition to watch mode the states of external pins are retained when the pin state setting bit in the standby control register STBC SPL is 0 and the states of external pins become high impedance when that bit is 1 those pins are pulled up for which pull up resistor con...

Page 90: ...in Figure 6 9 2 connect the external clock to the X0 pin while leaving the X1 pin open To supply the subclock from an external source connect the external clock to the X0A pin while leaving the X1A pin open Figure 6 9 2 Sample Connections of External Clocks X0 1X X0A X1A 63 I N T13 X0A P64 X1 Main clock oscillator circuit Subclock oscillator circuit Main clock oscillator circuit Two system clock p...

Page 91: ...sing subclock oscillation on a two system clock product and it enters subclock mode for some reason there is no solution to recovering its operation as there is no clock supply available If you use the main clock alone therefore be sure to select a single system clock product ...

Page 92: ...e machine clock MCLK that drives the CPU and the count clock 27 FCH or 28 FCH output from of the time base timer The count clock source is a clock frequency divided by the prescaler or a buffered clock used by the peripheral resources listed below Note that the prescaler has no control register and operates continuously driven by the machine clock MCLK and the count clock 27 FCH or 28 FCH of the t...

Page 93: ...eripheral resources The circuit also buffers the clock from the timebase timer 27 FCH and 28 FCH and supplies it to the peripheral resources Input Clock The prescaler uses the machine clock or the clock output from the timebase timer as the input clock Output Clock The prescaler supplies clocks to the 8 10 bit composite timer 16 bit PPG timer UART SIO dedicated baud rate generator and 10 bit A D c...

Page 94: ...e clock and timebase timer clocks are supplied Table 6 12 1 lists the count clock sources generated by the prescaler Table 6 12 1 Count Clock Sources Generated by Prescaler Count Clock Source Cycle Cycle FCH 10MHz MCLK 10MHz Cycle FCH 16MHz MCLK 16MHz Cycle FCH 16 25MHz MCLK 16 25MHz 2 MCLK MCLK 2 5MHz MCLK 2 8MHz MCLK 2 8 125MHz 4 MCLK MCLK 4 2 5MHz MCLK 4 4MHz MCLK 4 4 0625MHz 8 MCLK MCLK 8 1 25...

Page 95: ...diately after they are activated may involve an error of up to one cycle of the clock source captured by the resource depending on the prescaler output value Figure 6 13 1 Clock Capturing Error Immediately after Activation of Peripheral Resources The prescaler count value affects the following resources UART SIO 8 16 bit composite timer 16 bit PPG 10 bit A D converter Prescaler output Resource act...

Page 96: ...82 CHAPTER 6 CLOCK CONTROLLER ...

Page 97: ...83 CHAPTER 7 RESET This section describes the reset operation 7 1 Reset Operation 7 2 Reset Source Register RSRR ...

Page 98: ...ration with an external clock Note however that external pins including I O ports and peripheral resources are reset asynchronously Additionally there are standard pulse width values for external reset input If the value is below the standard the reset may not be accepted The standard value is listed on the data sheet Please design your external reset circuit so that this standard is met Software ...

Page 99: ... board RC oscillation circuit is supplied internally See CHAPTER 26 CLOCK SUPERVISOR for details about the clock supervisor Reset Time In the case of a software reset or watchdog reset the reset time consists of a total of three machine clock cycles one machine clock cycle at the machine clock frequency selected before the reset and two machine clock cycles at the machine clock frequency initially...

Page 100: ...access has ended This function prevents a word data write operation from being cut off by a reset after one byte Pin State During a Reset When a reset occurs all of the I O ports and peripheral resource pins remain in a high impedance state until setup is performed by software after the reset is released External reset input Software reset Watchdog reset Power on reset low voltage detection reset ...

Page 101: ...87 CHAPTER 7 RESET Note Connect a pull up resistor to those pins which remain at high impedance during a reset to prevent the devices the pins from malfunctioning ...

Page 102: ...tchdog reset flag bit WDTR Read Write 0 1 Factor is watchdog reset Operation is not affected External reset flag bit EXTS Read Write 0 1 Factor is external reset Operation is not affected SWR HWR PONR WDTR EXTS HWDR 0009H Address Bit0 Initial value xxxxxxxxB R WX R WX R0 WX R WX R WX R WX R WX R WX Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 R0 WX Undefined bit Read value is 0 writting has no effect on ope...

Page 103: ...bit retains the value existing before the reset occurred Read access to this bit sets it to 0 The bit is read only Any value written is meaningless bit3 WDTR Watchdog reset flag bit This bit is set to 1 to indicate that a watchdog reset has occurred Otherwise the bit retains the value existing before the reset occurred Read access to this bit sets it to 0 The bit is read only Any value written is ...

Page 104: ...90 CHAPTER 7 RESET ...

Page 105: ...91 CHAPTER 8 INTERRUPTS This chapter explains the interrupts 8 1 Interrupts ...

Page 106: ...us Interrupt requests also release the device from standby mode to resume instruction execution Interrupt Requests from Peripheral Resources When an interrupt is accepted a branch to the interrupt service routine takes place with the content of the interrupt vector table address corresponding to the interrupt request as the address of the branch destination The priority for each interrupt request ...

Page 107: ...FFF6H FFF7H L02 1 0 IRQ3 FFF4H FFF5H L03 1 0 IRQ4 FFF2H FFF3H L04 1 0 IRQ5 FFF0H FFF1H L05 1 0 IRQ6 FFEEH FFEFH L06 1 0 IRQ7 FFECH FFEDH L07 1 0 IRQ8 FFEAH FFEBH L08 1 0 IRQ9 FFE8H FFE9H L09 1 0 IRQ10 FFE6H FFE7H L10 1 0 IRQ11 FFE4H FFE5H L11 1 0 IRQ12 FFE2H FFE3H L12 1 0 IRQ13 FFE0H FFE1H L13 1 0 IRQ14 FFDEH FFDFH L14 1 0 IRQ15 FFDCH FFDDH L15 1 0 IRQ16 FFDAH FFDBH L16 1 0 IRQ17 FFD8H FFD9H L17 1...

Page 108: ...CCR IL1 IL0 When interrupt level 3 is set for an interrupt request the CPU ignores the interrupt request Table 8 1 2 shows the relationships between interrupt level setting bits and interrupt levels XX 0 to 23 Corresponding interrupt number During execution of a main program usually the interrupt level bits in the condition code register CCR IL1 IL0 contain 11B Register Address bit7 bit6 bit5 bit4...

Page 109: ...aluation of the interrupt enable flag CCR I Figure 8 1 2 illustrates the steps to take for interrupt processing Figure 8 1 2 Interrupt Processing Steps Interrupt from peripheral resource Peripheral resource interrupt request output enabled Check interrupt priority and transfer interrupt level to CPU Compare interrupt level with IL bit START Run main program Restore PC and PS Initialize peripheral ...

Page 110: ...with the same interrupt level occurs simultaneously is also determined at this time 5 If the received interrupt level or priority is lower than the level set in the interrupt level bits in the condition code register CCR IL1 IL0 the CPU checks the content of the interrupt enable flag CCR I and if interrupts are enabled CCR I 1 accepts the interrupt 6 The CPU pushes the contents of the program coun...

Page 111: ... code register CCR IL1 IL0 hold the same value as that of the interrupt level setting registers ILR0 to ILR5 corresponding to the current timer interrupt level 2 in this example If an interrupt request with a higher priority interrupt level level 1 in the example occurs the higher priority interrupt is processed preferentially To temporarily disable nested interrupt processing while a timer interr...

Page 112: ...chine clock cycles starts executing Interrupt handling time After receiving an interrupt the CPU requires 9 machine clock cycles to perform the following interrupt processing setup Saves the program counter PC and program status PS values Sets the PC to the start address interrupt vector of interrupt service routine Updates the interrupt level bits PS CCR IL1 IL0 in the program status PS register ...

Page 113: ...RETI is executed to end interrupt processing the program status PS and then the program counter PC are restored from the stack in the reverse order from which they were saved to the stack when interrupt processing started This restores the PS and PC values to their states prior to starting interrupt processing Note As the accumulator A and temporary accumulator T are not saved onto the stack autom...

Page 114: ... RAM address and allocate data areas starting from the minimum RAM address Figure 8 1 6 shows an example of setting the stack area Figure 8 1 6 Setting Example of Interrupt Processing Stack Area Note The stack area is allocated in descending order of addresses for interrupts subroutine calls and the PUSHW instruction it is deallocated in ascending order of addresses for return PETI RET and POPW in...

Page 115: ...I O PORT This chapter describes the functions and operations of the I O ports 9 1 Overview of I O Ports 9 2 Port 0 9 3 Port 1 9 4 Port 4 9 5 Port 5 9 6 Port 6 9 7 Port 9 9 8 Port A 9 9 Port B 9 10 Port C 9 11 Port E ...

Page 116: ...DR4 R W 00000000B Port 5 data register PDR5 R RM W 00000000B Port 5 direction register DDR5 R W 00000000B Port 6 data register PDR6 R RM W 00000000B Port 6 direction register DDR6 R W 00000000B Port 9 data register PDR9 R RM W 00000000B Port 9 direction register DDR9 R W 00000000B Port A data register PDRA R RM W 00000000B Port A direction register DDRA R W 00000000B Port B data register PDRB R RM...

Page 117: ...3 CHAPTER 9 I O PORT R W Readable writable Read value is the same as the write value R RM W Readable writable Read value is different from write value write value is read by read modify write instruction ...

Page 118: ...ysteresis analog Automotive CMOS AN00 analog input P01 INT01 AN01 P01 general purpose I O INT01 external interrupt input Hysteresis analog Automotive CMOS AN01 analog input P02 INT02 AN02 P02 general purpose I O INT02 external interrupt input Hysteresis analog Automotive CMOS AN02 analog input P03 INT03 AN03 P03 general purpose I O INT03 external interrupt input Hysteresis analog Automotive CMOS A...

Page 119: ...tion input enable Peripheral function input Pin Stop watch SPL 1 At bit operation instruction A D analog input Pull up ILSR2 read ILSR2 write ILSR2 Hysteresis Automotive Internal bus PDR read PDR write PDR DDR read DDR write DDR AIDRL read AIDRL write AIDRL 0 1 Peripheral function input enable Peripheral function input Pin Stop watch SPL 1 At bit operation instruction A D analog input ILSR2 read I...

Page 120: ...t port outputs L level 1 Pin state is H level PDR value is 1 As output port outputs H level DDR0 0 Port input enabled 1 Port output enabled PUL0 0 Pull up disabled 1 Pull up enabled AIDRL 0 Analog input enabled 1 Port input enabled ILSR2 0 Hysteresis input level 1 Automotive input level Table 9 2 3 Correspondence Between Registers and Pins for Port 0 Correspondence between related register bits an...

Page 121: ...utput latch but not output to the pin Reading the PDR returns the pin value However the read modify write command returns the PDR value Operation as a peripheral function output Setting the output enable bit of a peripheral function sets the corresponding pin as a peripheral function output The pin value can be read from the PDR register even if the peripheral function output is enabled Therefore ...

Page 122: ...et the AIDRL bit to 0 For other peripheral functions sharing pins disable its output Also write also the corresponding PUL bit to 0 Operation as LCDC segment output Set the DDR register bit which is corresponding to the LCDC segment output pin to 0 For other peripheral functions sharing pins disable its output Select the common segment pin in LCDC enable registers LCDCE1 to 6 and then set the port...

Page 123: ... OD Open drain PU Pull up Table 9 3 1 Port 1 Pins Pin name Function Shared peripheral functions I O type Input Output OD PU P10 UI0 EC0 P10 general purpose I O UI0 UART SIO ch 0 data input Hysteresis Automotive CMOS CMOS EC0 8 16 bit composite timer ch 0 external clock input P11 UO0 TO01 P11 general purpose I O UO0 UART SIO ch 0 data output Hysteresis Automotive CMOS TO01 8 16 bit composite timer ...

Page 124: ...instruction Pull up ILSR read ILSR write ILSR CMOS ILSR2 read ILSR2 write ILSR2 Automotive Hysteresis Hysteresis input level select Automotive input level select CMOS input level select PDR read PDR write PDR DDR read DDR write DDR PUL read PUL write PUL 0 1 1 0 Peripheral function output Peripheral function output enable Peripheral function input enable Peripheral function input Pin Stop Watch SP...

Page 125: ...e PDR DDR read DDR write DDR 0 1 1 0 Peripheral function output Peripheral function output enable Peripheral function input enable Peripheral function input Pin Stop Watch SPL 1 Internal bus In bit operation instruction ILSR2 read ILSR2 write ILSR2 Hysteresis Automotive Only P13 is selectable ...

Page 126: ...DR value is 0 As output port outputs L level 1 Pin state is H level PDR value is 1 As output port outputs H level DDR1 0 Port input enabled 1 Port output enabled PUL1 0 Pull up disabled 1 Pull up enabled ILSR ILSR2 00 Hysteresis input level selection 01 Automotive input level selection 10 CMOS input level selection 11 Table 9 3 3 Correspondence Between Registers and Pins for Port 1 Correspondence ...

Page 127: ...ing the PDR returns the pin value However the read modify write command returns the PDR value Operation as a peripheral function output Setting the output enable bit of a peripheral function sets the corresponding pin as a peripheral function output The pin value can be read from the PDR register even if the peripheral function output is enabled Therefore the output value of a peripheral function ...

Page 128: ...anges port 1 except P10 from the hysteresis input level to the automotive input level When the bit 1 of ILSR2 is 0 it should be the hysteresis input level The input level of P10 is determined by the bit0 of ILSR and bit1 of ILSR2 When bit0 of ILSR is 1 ignoring the bit1 of ILSR2 s value P10 should be CMOS input level When bit0 of ILSR is 0 if bit1 of ILSR2 is 0 P10 should be hysteresis input level...

Page 129: ...egister DDR4 Input level selection register ILSR2 Port 4 Pins Port 4 has four I O pins Table 9 4 1 lists the port 4 pins OD Open drain PU Pull up Table 9 4 1 Port 4 Pins Pin name Function Shared peripheral functions I O type Input Output OD PU P40 PPG2 P40 general purpose I O PPG2 16 bit PPG 2 output Hysteresis Automotive CMOS P41 PPG3 P41 general purpose I O PPG3 16 bit PPG 3 output Hysteresis Au...

Page 130: ... 4 1 Block Diagram of Port 4 PDR read PDR write PDR DDR read DDR write DDR 0 1 1 0 Peripheral function output Peripheral function output enable Pin Stop Watch SPL 1 Internal bus In bit operation instruction ILSR2 read ILSR2 write ILSR2 Hysteresis Automotive ...

Page 131: ...on Register name Data Read Read read modify write Write PDR4 0 Pin state is L level PDR value is 0 As output port outputs L level 1 Pin state is H level PDR value is 1 As output port outputs H level DDR4 0 Port input enabled 1 Port output enabled ILSR2 0 Hysteresis input level 1 Automotive input level Table 9 4 3 Correspondence Between Registers and Pins for Port 4 Correspondence between related r...

Page 132: ...sets the corresponding pin as a peripheral function output The pin value can be read from the PDR register even if the peripheral function output is enabled Therefore the output value of a peripheral function can be read by the read operation on PDR register However the read modify write command returns the PDR value Operation at reset Resetting the CPU initializes the DDR value to 0 and sets the ...

Page 133: ... Z High impedance Input disabled means the state that the operation of the input gate close to the pin is disabled Table 9 4 4 Pin State of Port 4 Operating state Normal operation Sleep Stop SPL 0 Watch SPL 0 Stop SPL 1 Watch SPL 1 At reset Pin state I O port analog input Hi Z the pull up setting is enabled Input cutoff Hi Z Input disabled ...

Page 134: ...heral function I O pins Port 5 data register PDR5 Port 5 direction register DDR5 Input level selection register ILSR Input level selection register 2 ILSR2 Port 5 Pins Port 5 has two I O pins Table 9 5 1 lists the port 5 pins OD Open drain PU Pull up Table 9 5 1 Port 5 Pins Pin name Function Shared peripheral functions I O type Input Output OD PU P50 SCL0 P50 general purpose I O SCL0 I2C ch 0 cloc...

Page 135: ... write ILSR 0 1 1 0 Peripheral function output Peripheral function output enable Peripheral function input enable Peripheral function input Stop Watch SPL 1 Internal bus In bit operation instruction Pin OD Hysteresis CMOS ILSR2 read ILSR2 write ILSR2 Hysteresis input level select Automotive input level select CMOS input level select Automotive ...

Page 136: ...me Data Read Read read modify write Write PDR5 0 Pin state is L level PDR value is 0 As output port outputs L level 1 Pin state is H level PDR value is 1 As output port outputs H level DDR5 0 Port input enabled 1 Port output enabled ILSR ILSR2 00 Hysteresis input level selection 01 Automotive input level selection 10 CMOS input level selection 11 Table 9 5 3 Correspondence Between Registers and Pi...

Page 137: ...ing the PDR returns the pin value However the read modify write command returns the PDR value Operation as a peripheral function output Setting the output enable bit of a peripheral function sets the corresponding pin as a peripheral function output The pin value can be read from the PDR register even if the peripheral function output is enabled Therefore the output value of a peripheral function ...

Page 138: ...bit1 of ILSR2 s value P50 P51 should be CMOS input level When bit3 bit4 of ILSR is 0 if bit3 of ILSR2 is 0 P50 should be hysteresis input level otherwise P50 should be automotive input level if bit4 of ILSR2 is 0 P51 should be hysteresis input level otherwise P51 should be automotive input level Make sure that the input level for P51 and P50 is changed during the peripheral function I2C0 stopped T...

Page 139: ...ns Pin name Function Shared peripheral functions I O type Input Output OD PU P60 SEG16 P60 general purpose I O SEG16 LCDC SEG16 output Hysteresis Automotive CMOS LCD P61 SEG17 P61 general purpose I O SEG17 LCDC SEG17 output Hysteresis Automotive CMOS LCD P62 SEG18 TO10 P62 general purpose I O SEG18 LCDC SEG18 output TO10 8 16 bit composite timer 10 output Hysteresis Automotive CMOS LCD P63 SEG19 T...

Page 140: ...ite PDR DDR read DDR write DDR 0 1 1 0 Peripheral function output Peripheral function output enable Peripheral function input enable Peripheral function input Pin Stop Watch SPL 1 Internal bus In bit operation instruction ILSR2 read ILSR2 write ILSR2 Hysteresis Automotive LCD output enable LCD output ...

Page 141: ... modify write Write PDR6 0 Pin state is L level PDR value is 0 As output port outputs L level 1 Pin state is H level PDR value is 1 As output port outputs H level DDR6 0 Port input enabled 1 Port output enabled ILSR2 0 Hysteresis input level selection 1 Automotive input level selection Table 9 6 3 Correspondence Between Registers and Pins for Port 6 Correspondence between related register bits and...

Page 142: ...ns the PDR value Operation as a peripheral function output Setting the output enable bit of a peripheral function sets the corresponding pin as a peripheral function output The pin value can be read from the PDR register even if the peripheral function output is enabled Therefore the output value of a peripheral function can be read by the read operation on PDR register However the read modify wri...

Page 143: ...egment pin in LCDC enable registers LCDCE1 to 6 and then set the port input control bit PICTL in LCDC enable register LCDCE1 to 1 Operation of the input level selection register Writing 1 to the bit5 of ILSR2 changes Port 6 from the hysteresis input level to the automotive input level When the bit5 of ILSR2 is 0 it should be the hysteresis input level Table 9 6 4 shows the pin states of the port S...

Page 144: ... 9 7 1 lists the port 9 pins OD Open drain PU Pull up 1 For the single system product the general purpose port is used for the dual system the sub clock oscillation pin is used Table 9 7 1 Port 9 Pins Pin name Function Shared peripheral functions I O type Input Output OD PU P90 V3 P90 general purpose I O V3 LCDC V3 pin Hysteresis Automotive CMOS P91 V2 PPG7 P91 general purpose I O V2 LCDC V2 pin H...

Page 145: ...rite PDR DDR read DDR write DDR PUL read PUL write PUL 0 1 1 0 Peripheral function output Peripheral function output enable Peripheral function input Pin Stop Watch SPL 1 Internal bus In bit operation instruction Pull up Selectalbe only P94 and P95 ILSR2 read ILSR2 write ILSR2 Hysteresis Automotive ...

Page 146: ...e Write PDR9 0 Pin state is L level PDR value is 0 As output port outputs L level 1 Pin state is H level PDR value is 1 As output port outputs H level DDR9 0 Port input enabled 1 Port output enabled PUL9 0 Pull up disabled 1 Pull up enabled ILSR2 0 Hysteresis input level 1 Automotive input level Table 9 7 3 Correspondence Between Registers and Pins for Port 9 Correspondence between related registe...

Page 147: ...t Setting the output enable bit of a peripheral function sets the corresponding pin as a peripheral function output The pin value can be read from the PDR register even if the peripheral function output is enabled Therefore the output value of a peripheral function can be read by the read operation on PDR register However the read modify write command returns the PDR value Operation at reset For P...

Page 148: ...ification bit in standby control register STBC SPL Hi Z High impedance Input enabled means that the input function is enabled it requires the pull up or pull down operation or preventing leaks by external inputs Same as other ports when used as an output port Table 9 7 4 Pin State of Port 9 Operating state Normal operation Sleep Stop SPL 0 Watch SPL 0 Stop SPL 1 Watch SPL 1 At reset Pin state I O ...

Page 149: ...nput level selection register ILSR2 Port A Pins Port A has four I O pins Table 9 8 1 lists the port A pins OD Open drain PU Pull up Table 9 8 1 Port A Pins Pin name Function Shared peripheral functions I O type Input Output OD PU PA0 COM0 PA0 general purpose I O COM0 LCD COM0 output Hysteresis Automotive CMOS LCD PA1 COM1 PA1 general purpose I O COM1 LCD COM1 output Hysteresis Automotive CMOS LCD ...

Page 150: ...am of Port A Figure 9 8 1 Block Diagram of Port A PDR read PDR write PDR DDR read DDR write DDR 0 1 LCD enable LCD output Pin Stop watch SPL 1 At bit operation instruction Internal bus ILSR2 read ILSR2 ILSR2 write Hysteresis Automotive ...

Page 151: ...ead read modify write Write PDRA 0 Pin state is L level PDR value is 0 As output port outputs L level 1 Pin state is H level PDR value is 1 As output port outputs H level DDRA 0 Port input enabled 1 Port output enabled ILSR2 0 Hysteresis input level 1 Automotive input level Table 9 8 3 Correspondence Between Registers and Pins for Port A Correspondence between related register bits and pins Pin na...

Page 152: ...lues to 0 and sets the port input enabled Note that the pin sharing for the LCD output is set its port input disabled since the port input control bit PICTL in LCDC enable register LCDCE1 is set to 0 Operation in stop mode and watch mode If the pin state specification bit in the standby control register STBC SPL is set to 1 when the device switches to stop or watch mode the pin is set forcibly to ...

Page 153: ...r STBC SPL Hi Z High impedance Input enabled means the state that the operation of the input close to the pin is disabled Table 9 8 4 Pin State of Port A Operating state Normal operation Sleep Stop SPL 0 Watch SPL 0 Stop SPL 1 Watch SPL 1 At reset Pin state I O port peripheral function I O Hi Z Input cutoff Hi Z Input disabled ...

Page 154: ...pe Input Output OD PU PB0 SEG00 TPCLK CALPL PB0 general purpose I O SEG00 LCDC SEG0 output Hysteresis Automotive CMOS LCD TPCLK RTC TPCLK clock output CALPL RTC external reference clock input PB1 SEG01 PB1 general purpose I O SEG01 LCDC SEG1 output Hysteresis Automotive CMOS LCD PB2 SEG02 PB2 general purpose I O SEG02 LCDC SEG2 output Hysteresis Automotive CMOS LCD PB3 SEG03 PB3 general purpose I ...

Page 155: ... DDR read DDR write DDR 0 1 LCD enable LCD output Pin Stop watch SPL 1 At bit operation instruction Internal bus ILSR3 read ILSR3 ILSR3 write Hysteresis Automotive Peripheral function input Peripheral function input enable Peripheral function output enable Peripheral function output 0 1 Selectable only PB0 ...

Page 156: ...ify write Write PDRB 0 Pin state is L level PDR value is 0 As output port outputs L level 1 Pin state is H level PDR value is 1 As output port outputs H level DDRB 0 Port input enabled 1 Port output enabled ILSR3 0 Hysteresis input level 1 Automotive input level Table 9 9 3 Correspondence Between Registers and Pins for Port B Correspondence between related register bits and pins Pin name PB7 PB6 P...

Page 157: ...nd PICT bit of the LCDCE1 register are initialized to 0 and port input becomes disabled Operation in stop mode and watch mode After moving to stop mode or watch mode setting the standby control register pin state specification bit STBC SPL to 1 forces the pin into high impedance regardless of the value of the DDR register Note that input is locked to L and blocked in order to prevent leaks from fr...

Page 158: ...ll use Operation of the input level selection register Writing 1 to the bit0 of ILSR3 changes Port B from the hysteresis input level to the automotive input level When the bit0 of ILSR3 is 0 it should be the hysteresis input level Table 9 9 4 shows the pin states of the port SPL Pin state specification bit in standby control register STBC SPL Hi Z High impedance Input enabled means that the input ...

Page 159: ...nput Hysteresis Automotive CMOS LCD SEG08 LCDC SEG8 output PC1 SEG09 TRG1 PC1 general purpose I O SEG09 LCDC SEG9 output Hysteresis Automotive CMOS LCD TRG1 PPG trigger 1 input PC2 SEG10 TRG2 PC2 general purpose I O SEG10 LCDC SEG10 output Hysteresis Automotive CMOS LCD TRG2 PPG trigger 2 input PC3 SEG11 TRG3 PC3 general purpose I O SEG11 LCDC SEG11 output Hysteresis Automotive CMOS LCD TRG3 PPG t...

Page 160: ...ck Diagram of Port C PDR read PDR write PDR DDR read DDR write DDR 0 1 Pin Stop Watch SPL 1 Internal bus Peripheral function input enable Peripheral function input In bit operation instruction ILSR3 read ILSR3 ILSR3 write Hysteresis Automotive LCD output LCD enable ...

Page 161: ...dify write Write PDRC 0 Pin state is L level PDR value is 0 As output port outputs L level 1 Pin state is H level PDR value is 1 As output port outputs H level DDRC 0 Port input enabled 1 Port output enabled ILSR3 0 Hysteresis input level 1 Automotive input level Table 9 10 3 Correspondence Between Registers and Pins for Port C Correspondence between related register bits and pins Pin name PC7 PC6...

Page 162: ...LCDE1 to 0 and sets the port input disabled Operation in stop mode and watch mode After moving to stop mode or watch mode setting the standby control register pin state specification bit STBC SPL to 1 forces the pin into high impedance regardless of the value of the DDR register Note that input is locked to L and blocked in order to prevent leaks from freed input If however peripheral function inp...

Page 163: ...6 select all common pins and segment pins you will use Operation of the input level selection register Writing 1 to the bit1 of ILSR3 changes Port C from the hysteresis input level to the automotive input level When the bit1 of ILSR3 is 0 it should be the hysteresis input level Table 9 10 4 shows the pin states of the port SPL Pin state specification bit in standby control register STBC SPL Hi Z H...

Page 164: ...pins Table 9 11 1 lists the port E pins OD Open drain PU Pull up Table 9 11 1 Port E Pins Pin name Function Shared peripheral functions I O type Input Output OD PU PE4 INT10 SEG28 PE4 general purpose I O INT10 external interrupt input Hysteresis Automotive CMOS LCD SEG28 LCDC SEG28 output PE5 INT11 SEG29 PE5 general purpose I O INT11 external interrupt input Hysteresis Automotive CMOS LCD SEG29 LC...

Page 165: ...ck Diagram of Port E PDR read PDR write PDR DDR read DDR write DDR 0 1 LCD enable LCD output Pin Stop watch SPL 1 At bit operation instruction Internal bus ILSR3 read ILSR3 write ILSR3 Peripheral function input enable Peripheral function input Automotive Hysteresis ...

Page 166: ... name Data Read Read read modify write Write PDRE 0 Pin state is L level PDR value is 0 As output port outputs L level 1 Pin state is H level PDR value is 1 As output port outputs H level DDRE 0 Port input enabled 1 Port output enabled ILSR3 0 Hysteresis input level 1 Automotive input level Table 9 11 3 Correspondence Between Registers and Pins for Port E Correspondence between related register bi...

Page 167: ...DR values to 0 and sets the port input enabled Note that the pin sharing for the LCD output is set its port input disabled since the port input control bit PICTL in LCDC enable register LCDCE1 is set to 0 Operation in stop mode and watch mode If the pin state specification bit in the standby control register STBC SPL is set to 1 when the device switches to stop or watch mode the pin is set forcibl...

Page 168: ... automotive input level When the bit2 of ILSR3 is 0 it should be the hysteresis input level Table 9 11 4 shows the pin states of the port SPL Pin state specification bit in standby control register STBC SPL Hi Z High impedance Input enabled means the state that the operation of the input gate close to the pin is disabled Table 9 11 4 Pin State of Port E Operating state Normal operation Sleep Stop ...

Page 169: ...ns of the timebase timer 10 1 Overview of Timebase Timer 10 2 Configuration of Timebase Timer 10 3 Registers of the Timebase Timer 10 4 Interrupts of Timebase Timer 10 5 Explanation of Timebase Timer Operations and Setup Procedure Example 10 6 Precautions when Using Timebase Timer ...

Page 170: ...ng the main clock divided by two as the count clock The counter of the timebase timer counts down so that an interrupt request is generated every time the selected interval time elapses The interval time can be selected from the following four types Table 10 1 1 shows the interval times available to the timebase timer FCH Main source oscillation clock The values in parentheses represent the values...

Page 171: ...n clock operates at 4MHz Table 10 1 2 Clock Signal Supplied from the Timebase Timer Destination of Supply Clock Clock Cycle Remark Oscillation stabilization wait time of main clock 213 x 2 FCH 4 10 ms to 2 FCH 0 5 μs Set by oscillation stabilization wait time setting register WATR Oscillation stabilization wait time of main PLL clock 210 x 2 FCH 512 0 μs The time between 2 count Min and 3 count Ma...

Page 172: ...210 x 211 x 212 x 213 x 214 x 215 x 216 x 217 x 218 Timebase timer counter FCH divided by 2 Counter clear To prescaler To watchdog timer Counter clear circuit Interval timer selector TCLR TBC1 TBIF TBIE TBC0 Timebase timer control register TBTC Resets stops Main clock Watchdog timer clear Timebase timer interrupt 213 x 2 FCH to 2 FCH To clock control block oscillation stabilization wait time selec...

Page 173: ...p the timebase timer counter to use the interval timer Timebase timer control register TBTC This register selects the interval time clears the counter controls interrupts and checks the status Input Clock The timebase timer uses the main clock divided by two as its input clock count clock Output Clock The timebase timer supplies clocks to the main clock oscillation stabilization wait time timer th...

Page 174: ...160 CHAPTER 10 TIMEBASE TIMER ...

Page 175: ...ster Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 000AH TBIF TBIE TBC1 TBC0 TCLR 00000000B R RM1 W R W R0 WX R0 WX R0 WX R W R W R0 W R RM1 W Readable writable Read value is different from write value 1 is read by read modify write instruction R W Readable writable Read value is the same as write value R0 WX Undefined bit Read value is 0 writing has no effect on operation R0 W Wri...

Page 176: ...s 216 x 2 FCH 32 77 ms 0 1 TBIE Timebase timer interrupt request enable bit 0 Disables output of interrupt request 1 Enables output of interrupt request Timebase timer interrupt request flag bit TBIE Read Write 0 Interval time has not elapsed Clears bit 1 Interval time has elapsed No change No effect on operation Address 000AH TBIF TBIE TCLR TBC0 TBC1 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 Initia...

Page 177: ... enables output of timebase timer interrupt requests Interrupt request is outputted when this bit and the timebase timer interrupt request flag bit TBIF are set to 1 bit5 to bit3 Unused bits These bits are unused Read value is always 0 Write has no effect on the operation bit2 bit1 TBC1 TBC0 Interval time select bits These bits select interval time bit0 TCLR Timebase timer initialization bit This ...

Page 178: ...roller Regardless of the value of TBIE bit TBIF bit is set to 1 when the selected bit underflows When TBIF bit is set to 1 and TBIE bit is changed from the disable state to the enable state 0 1 an interrupt request is generated immediately TBIF bit is not set when the counter is cleared TBTC TCLR 1 and the timebase timer counter underflows at the same time Write 1 to TBIF bit to clear an interrupt...

Page 179: ... oscillation wait time derived from the transition to the clock mode or standby mode To prevent this set the timebase timer interrupt request enable bit of the timebase timer control register TBTC TBIE to 0 to disable interrupts of the timebase timer when entering a mode in which the main clock stops oscillating stop mode subclock mode or sub PLL clock mode Table 10 4 2 Register and Vector Table f...

Page 180: ...st is generated at each interval time selected based on the time when the counter was last cleared Clearing Timebase Timer If the timebase timer is cleared when the output of the timebase timer is used in other peripheral functions this will affect the operation by changing the count time or in other manners When clearing the counter by using the timebase timer initialization bit TBTC TCLR perform...

Page 181: ...top mode the timebase timer is used to count the oscillation stabilization wait time Figure 10 5 2 Operations of Timebase Timer TBIF bit TBIE bit 2 SLP bit STBC register 3 STP bit STBC register Counter value count down Clear by transferring to stop mode 000000 Oscillation stabilization wait time 1 Power on reset Interval cycle TBTC TBC1 0 11 3FFFFF Clear in interrupt processing routine Sleep Stop ...

Page 182: ...ase timer is set up in the following procedure 1 Disable interrupts TBTC TBIE 0 2 Set the interval time TBTC TBC1 0 3 Enable interrupts TBTC TBIE 1 4 Clear the counter TBTC TCLR 1 Processing interrupts 1 Clear the interrupt request flag TBTC TBIF 0 2 Clear the counter TBTC TCLR 1 ...

Page 183: ...so when the oscillation stabilization wait time is required for the main clock When the timebase timer is selected for the count clock of the watchdog timer WDTC CSI 0 00 or CSI 01 clearing the timebase timer also clears the watchdog timer Peripheral functions receiving clock from timebase timer In the mode where the source oscillation of the main clock is stopped the counter is cleared and the ti...

Page 184: ...170 CHAPTER 10 TIMEBASE TIMER ...

Page 185: ...ions and operations of the watchdog timer 11 1 Overview of Watchdog Timer 11 2 Configuration of Watchdog Timer 11 3 Registers of the Watchdog Timer 11 4 Explanation of Watchdog Timer Operations and Setup Procedure Example 11 5 Precautions when Using Watchdog Timer ...

Page 186: ...ount clock for the watchdog timer The interval times of the watchdog timer are shown in Table 11 1 1 If the counter of the watchdog timer is not cleared a watchdog reset is generated between the minimum time and the maximum time Clear the counter of the watchdog timer within the minimum time WDTC CS1 0 Count clock switch bit of watchdog timer control register For information about the minimum and ...

Page 187: ...1 Block Diagram of Watchdog Timer CS1 CS0 WTE3 WTE2 WTE0 WTE1 Count clock selector Watchdog timer clear selector Counter clear control circuit Reset control circuit Clear signal from timebase timer Clear signal from watch prescaler Sleep mode starts Stop mode starts Timebase timer watch mode starts FCH Main clock FCL Subclock 213 x 2 FCH 212 x 2 FCH Watch prescaler output 220 x 2 FCH 219 x 2 FCH T...

Page 188: ...the watchdog timer counter overflows Watchdog timer clear selector This selector selects the watchdog timer clear signal Counter clear control circuit This circuit controls the clearing and stopping of the watchdog timer counter Watchdog timer control register WDTC This register performs setup for activating clearing the watchdog timer counter as well as for selecting the count clock Input Clock T...

Page 189: ...of The Watchdog Timer Watchdog timer control register WDTC Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 000CH CS1 CS0 WTE3 WTE2 WTE1 WTE0 00 0000B R W R W R0 WX R0 WX R0 W R0 W R0 W R0 W R W Readable writable Read value is the same as write value R0 WX Undefined bit Read value is 0 writing has no effect on operation R0 W Write only Writable 0 is read Not used ...

Page 190: ...Other than above No effect on operation CS1 CS0 Count clock switch bits 0 0 Output cycle of timebase timer 221 FCH 0 Output cycle of timebase timer 220 FCH 1 Output cycle of watch prescaler 214 FCL 1 1 0 1 Output cycle of watch prescaler 213 FCL Address 000CH bit5 bit6 CS0 R W bit7 CS1 R W bit4 R0 WX R0 WX bit3 WTE3 bit2 WTE2 bit1 WTE1 bit0 WTE0 R0 W R0 W R0 W R0 W Initial value 00 0000B FCH Main ...

Page 191: ...s the timebase timer is stopped in these modes Do not select the output of the watch prescaler in single system clock product bit5 bit4 Unused bits These bits are not used The read value is 00 Write has no effect on operation bit3 to bit0 WTE3 WTE2 WTE1 WTE0 Watchdog control bits These bits are used to control the watchdog timer Writing 0101B activates the watchdog timer in first write after reset...

Page 192: ... it overflows allowing the watchdog timer to generate a watchdog reset The counter of the watchdog timer is cleared when 0101B is written to the watchdog control bits of the watchdog timer control register WDTC WTE3 to WTE0 for the second or any succeeding time The watchdog timer is cleared at the same time as the timer selected as the count clock timebase timer or watch prescaler is cleared Opera...

Page 193: ...ted in the subclock mode the timer starts operating in the main clock mode after the oscillation stabilization wait time has elapsed The reset signal is outputted during this oscillation stabilization wait time Setup Procedure Example The watchdog timer is set up in the following procedure 1 Select the count clock WDTC CS1 CS0 2 Activate the watchdog timer WDTC WTE3 to WTE0 0101B 3 Clear the watch...

Page 194: ...ce the timer is activated In the subclock mode the timebase timer does not operate because the main clock stops oscillating In order to operate the watchdog timer in the subclock mode it is necessary to select the watch prescaler as the count clock beforehand and set WDTC CS1 0 to 10B or 11B Clearing the watchdog timer Clearing the counter used for the count clock of the watchdog timer timebase ti...

Page 195: ...the hardware watchdog timer 12 1 Overview of Hardware Watchdog Timer 12 2 Configuration of Hardware Watchdog Timer 12 3 Registers of the Hardware Watchdog Timer 12 4 Explanation of Hardware Watchdog Timer Operations and Setup Procedure Example 12 5 Precautions when Using Hardware Watchdog Timer ...

Page 196: ...ck for the hardware watchdog timer Table 12 1 1 shows the minimum and maximum frequency of RC oscillator The interval times of the hardware watchdog timer are shown in Table 12 1 2 If the counter of the hardware watchdog timer is not cleared a hardware watchdog reset is generated between the minimum time and the maximum time Clear the counter of the hardware watchdog timer within the minimum time ...

Page 197: ...hdog timer control register HWDC Block Diagram of Hardware Watchdog Timer Figure 12 2 1 Block Diagram of Hardware Watchdog Timer Reserved WTE3 WTE2 WTE0 WTE1 RC oscillator Prescalar Counter clear control circuit Reset control circuit Sleep mode starts Stop mode starts Timebase timer watch mode starts FCH Main clock FCL Sub clock RC oscillator clock Hardware timer counter RST Overflow Watchdog time...

Page 198: ... when the hardware watchdog timer counter overflows Hardware watchdog timer clear selector This selector selects the hardware watchdog timer clear signal Counter clear control circuit This circuit controls the clearing and stopping of the hardware watchdog timer counter Hardware watchdog timer control register HWDC This register performs setup for activating clearing the hardware watchdog timer co...

Page 199: ... Timer Hardware Watchdog timer control register HWDC Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 000DH Reserved Reserved WTE3 WTE2 WTE1 WTE0 00000000B R0 WX R0 WX R0 WX R0 WX R0 W R0 W R0 W R0 W R W Readable writable Read value is the same as write value R0 W0 Reserved bit Always write 0 Read value is 0 R0 WX Undefined bit Read value is 0 writing has no effect on operation R0 W W...

Page 200: ... WTE2 WTE1 WTE0 Watchdog control bits 1 0 Clear watchdog timer Other than above No effect on operation Address 000DH bit5 bit6 bit7 R0 WX bit4 R0 WX R0 WX bit3 WTE3 Reserved bit2 WTE2 bit1 WTE1 bit0 WTE0 R0 W R0 W R0 W R0 W Initial value 00000000 B CH CL R W Readable writable Read value is the same as write value R0 WX Undefined bit Read value is 0 writing has no effect on operation R0 W0 Reserved...

Page 201: ...ue is 00 Write has no effect on operation bit5 Reserved bit These bits are reserved Write has no effect on operation Read value is 0 bit4 Reserved bit These bits are reserved Write has no effect on operation Read value is 0 bit3 to bit0 WTE3 WTE2 WTE1 WTE0 Watchdog control bits These bits are used to control the hardware watchdog timer Writing 0101B clear the hardware watchdog timer Writing other ...

Page 202: ...e watchdog timer is cleared when 0101B is written to the hardware watchdog control bits of the watchdog timer control register HWDC WTE3 to WTE0 for the second or any succeeding time The hardware watchdog timer is cleared at the same time as the timer selected as the count clock from RC oscillator prescalar is cleared Operation in standby mode Regardless of the clock mode selected the hardware wat...

Page 203: ...ed in the subclock mode the timer starts operating in the main clock mode after the oscillation stabilization wait time has elapsed The reset signal is outputted during this oscillation stabilization wait time Setup Procedure Example The hardware watchdog timer is set up in the following procedure Clear the hardware watchdog timer HWDC WTE3 to WTE0 0101B RC oscillator prescalar output Watchdog 1 b...

Page 204: ...Therefore after reset the hardware watchdog timer must be cleared within timer interval Clearing the hardware watchdog timer Clearing the RC oscillator prescalar also clears the counter of the hardware watchdog timer The counter of the hardware watchdog timer is cleared when entering the sleep mode stop mode or watch mode Programming precaution When creating a program in which the hardware watchdo...

Page 205: ...r 13 1 Overview of Watch Prescaler 13 2 Configuration of Watch Prescaler 13 3 Registers of the Watch Prescaler 13 4 Interrupts of Watch Prescaler 13 5 Explanation of Watch Prescaler Operations and Setup Procedure Example 13 6 Precautions when Using Watch Prescaler 13 7 Sample Programs for Watch Prescaler ...

Page 206: ... as its count clock The counter of the watch prescaler counts down and an interrupt request is generated every time the selected interval time has elapsed The interval time can be selected from the following four types Table 13 1 1 shows the interval times of the watch prescaler FCL Subclock The values in parentheses represent the values achieved when the subclock operates at 32 768kHz Note The wa...

Page 207: ...23 x 24 x 25 x 26 x 27 x 28 x 29 x 210 x 211 x 212 x 213 x 214 x 215 Counter clear circuit Interval timer selector WTIF WTIE WTC1 WTC0 WCLR Watch prescaler counter counter To oscillation stabilization wait timer of subclosk watchdog timer watch counter Watch prescaler control register WPCR 215 2 FCL to 21 2 FCL To clock control oscillation stabilization wait time selector Resets stops Subclock Int...

Page 208: ...our bits used for the interval timer among 15 bits available in the watch prescaler counter Watch prescaler control register WPCR This register selects the interval time clears the counter controls interrupts and checks the status Input Clock The watch prescaler uses the subclock divided by two as its input clock count clock Output Clock The watch prescaler supplies its clock to the timer for the ...

Page 209: ...ddress bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 000BH WTIF WTIE WTC1 WTC0 WCLR 00000000B R RM1 W R W R0 WX R0 WX R0 WX R W R W R0 W R RM1 W Readable writable Read value is different from write value 1 is read by read modify write instruction R W Readable writable Read value is the same as write value R0 WX Undefined bit Read value is 0 writing has no effect on operation R0 W Write onl...

Page 210: ...250ms 213 2 FCL 500ms 214 2 FCL 1 00s 0 1 1 1 0 1 WTIE Interrupt request enable bit 0 Disables interrupt request output 1 Enables interrupt request output Watch interrupt request flag bit WTIF Read Write 0 Interval time has not elapsed Clears the bit 1 Interval time has elapsed No change No effect on operation Address 000BH bit7 R RM1 W WTIF bit6 WTIE bit5 bit4 bit3 R0 WX R0 WX R0 WX bit2 WTC1 bit...

Page 211: ...ables the interrupt request output of the watch prescaler Interrupt requests are outputted when this bit and the watch interrupt request flag bit WTIF are set to 1 bit5 to bit3 Unused bits These bits are not used The read value is always 0 Write has no effect on the operation bit2 bit1 WTC1 WTC0 Watch interrupt interval time select bits These bits select the interval time bit0 WCLR Watch timer ini...

Page 212: ...te to the enable state WPCR WTIE 0 1 immediately generates an interrupt request The WTIF bit cannot be set when the counter is cleared WPCR WCLR 1 at the same time as the selected bit overflows Write 0 to the WTIF bit in the interrupt processing routine to clear an interrupt request to 0 Note When enabling the output of interrupt requests WPCR WTIE 1 after canceling a reset always clear the WTIF b...

Page 213: ... the oscillation stabilization wait time of the subclock required for recovery by an external interrupt upon the transition from the subclock mode or the sub PLL clock mode to the stop mode To prevent this set the interrupt request enable bit WPCR WTIE in the watch prescaler control register to 0 to disable interrupts of the watch prescaler when entering the stop mode during the subclock mode or t...

Page 214: ...ization bit WTCR WCLR perform setup so that this does not have unexpected effects on other peripheral functions When the output of the watch prescaler is selected as the count clock clearing the watch prescaler also clears the watchdog timer The watch prescaler is cleared not only by the watch prescaler initialization bit WTCR WCLR but also when the subclock is stopped and a count is required for ...

Page 215: ...led by watch interrupt WIRQ Stop cancelled by external interrupt When setting interval time select bits in the watch prescaler control register WPCR WTC1 0 to 11 2 14 x 2 FCL Count value detected in WPCR WTC1 0 Count value detected in WATR SWT3 2 1 0 4 Counter clear WPCR WCLR 1 Subclock oscillation stabilization wait time Clear in interrupt processing routine WPCR WTC1 0W Interval time select bits...

Page 216: ...escaler When the watch prescaler is selected as the count clock of the watchdog timer WDTC CS1 0 10 or CS1 0 11 clearing the watch prescaler also clears the watchdog timer Watch interrupts In the main stop mode the watch prescaler performs counting but does not generate the watch prescaler interrupts IRQ20 Peripheral functions receiving clock from the watch prescaler If the watch prescaler is clea...

Page 217: ...he following table is used to select the interrupt level How to enable disable clear interrupts Interrupt request enable flag Interrupt request flag The interrupt request enable bit WPCR WTIE is used to enable interrupts The watch interrupt request flag WPCR WTIF is used to clear interrupt requests What to be controlled Watch timer initialization bit WCLR When initializing watch prescaler Set the ...

Page 218: ...204 CHAPTER 13 WATCH PRESCALER ...

Page 219: ... counter 14 1 Overview of Watch Counter 14 2 Configuration of Watch Counter 14 3 Registers of Watch Counter 14 4 Interrupts of Watch Counter 14 5 Explanation of Watch Counter Operations and Setup Procedure Example 14 6 Precautions when Using Watch Counter 14 7 Sample Programs for Watch Counter ...

Page 220: ...unt clock and generates an interrupt request The count clock can be selected from the four types shown in Table 14 1 1 The count value can be set to any number from 0 to 63 When 0 is selected no interrupt is generated When the count clock is set to 1s and the count value is set to 60 an interrupt is generated every one minute FCL Subclock Table 14 1 1 Count Clock Types Count clock Count cycle when...

Page 221: ...ternal bus ISEL WCFLG CTR5 CTR4 CTR3 CTR2 CTR1 CTR0 CS1 CS0 RCTR5 RCTR4 RCTR3 RCTR2 RCTR1 RCTR0 Counter 6 bit counter Counter clear Watch counter control register WCSR Watch counter data register WCDR Underflow Reload value Counter value Counter clock selected From watch prescaler 2 FCL 2 FCL 2 FCL 2 FCL 12 13 14 15 Interrupt enabled FCL Subclock Interrupt of watch prescaler Interrupt of watch cou...

Page 222: ...r as its count clock Watch counter control register WCSR This register controls interrupts and checks the status Watch counter data register WCDR This register sets the interval time and selects the count clock Input Clock The watch counter uses the output clock of the watch prescaler as its input clock count clock ...

Page 223: ...egister WCDR Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 0FE3H CS1 CS0 RCTR5 RCTR4 RCTR3 RCTR2 RCTR1 RCTR0 00111111B R W R W R W R W R W R W R W R W Watch counter control register WCSR Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 0070H ISEL WCFLG CTR5 CTR4 CTR3 CTR2 CTR1 CTR0 00000000B R W R W R W R W R W R W R W R W R W Readable writable Read value is the same a...

Page 224: ...gister WCDR R W bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00111111B Initial value CS1 CS0 RCTR4 RCTR2 RCTR1RCTR0 RCTR5 R W RCTR3 Initial value R W Readable writable Read value is the same as write value FCL Subclock CS1 0 0 1 1 CS0 0 1 0 1 RCTR5 to RCTR0 These bits set the counter reload value Initial value 3FH Count clock select bits FCL 32 768kHz 2 FCL 125ms 2 FCL 250ms 2 FCL 500ms 2 FCL 1s 12 13 ...

Page 225: ...t0 RCTR5 to 0 Counter reload value setting bits These bits set the counter reload value If the value is modified during counting the modified value will become effective upon a reload after the counter underflows Writing 0 generates no interrupt request If the reload value RCTR5 to RCTR0 is modified at the same time as an interrupt is generated WCSR WCFLG 1 the correct value will not be reloaded T...

Page 226: ...ad only Readable writting has no effect on operation R RM1 W Readable writable Read value is different from write value 1 is read by read modfy write instruction 0 1 R W R RM1 W R WX R WX R WX R WX CTR5 to CTR0 These bits can read the counter value Read No interrupt request generated An interrupt request generated ISEL 0 1 Watch counter start interrupt enable bit Stops watch counter and disables i...

Page 227: ...o 1 to select interrupts of the watch counter The watch counter performs counting using an asynchronous clock from the watch prescaler For this reason an error of up to one count clock may occur at the beginning of a count cycle depending on the timing for setting ISEL bit to 1 bit6 WCFLG Interrupt request flag bit This bit is set to 1 when the counter underflows When this bit and the ISEL bit are...

Page 228: ...h counter Register and Vector Table Related to Interrupts of Watch Counter CHAPTER 8 INTERRUPTS describes the interrupt request numbers and vector tables of all peripheral functions The watch counter shares the same interrupt request number and vector table as the watch prescaler Table 14 4 1 Interrupt Control Bits and Interrupt Sources of Watch Timer Item Description Interrupt request flag bit WC...

Page 229: ...rt a down count and enable interrupts Also disable interrupts of the watch prescaler The watch counter performs counting by using a divided clock asynchronous from the watch prescaler An error of up to one count clock may occur at the beginning of a count cycle depending on the timing for setting the ISEL bit to 1 3 When the counter underflows the WCFLG bit of the WCSR register is set to 1 generat...

Page 230: ...fore use In any standby mode other than the sub stop mode the watch counter continues to operate Operation at the Main Stop Mode The interrupt is not generated though the clock counter continues the count operation when entering the main stop mode Moreover the clock counter stops too when subclock oscillation stop bit SYCC SUBS of the system clock control register is set to 1 Setup Procedure Examp...

Page 231: ...ared during the operation of the watch counter the watch counter may not be able to perform normal operation When clearing the watch prescaler set the ISEL bit of the WCSR register to 0 to stop the watch counter in advance When the operation is reactivated by WCSR ISEL 0 after counter stop please reactivate after confirming reading WCSR CTR 5 0 twice and clearing to CTR 5 0 000000B ...

Page 232: ...ollowing table How to enable disable clear interrupts Interrupt request enable flag Interrupt request flag The interrupt request enable bit WCSR ISEL is used to enable interrupts The interrupt request flag WCSR WCFLG is used to clear interrupt requests What to be controlled Watch timer initialization bit ISEL When enabling watch counter Set the bit to 1 When stopping watch counter Set the bit to 0...

Page 233: ...describes the functions and operations of the wild register 15 1 Overview of Wild Register 15 2 Configuration of Wild Register 15 3 Registers of Wild Register 15 4 Operating Description of Wild Register 15 5 Typical Hardware Connection Example ...

Page 234: ...he wild register consists of three data setting registers three upper address setting registers three lower address setting registers a 1 byte address compare enable register and a 1 byte data test register You can substitute new data at specific addresses by specifying the addresses and data in these registers Up to three bytes of data can be set in the three data setting registers Similarly up t...

Page 235: ...r WREN Wild register data test setup register WROR Control circuit block Block Diagram of Wild Register Function Figure 15 2 1 Block Diagram of Wild Register Function Access control circuit Address compare circuit Decoder and logic control circuit Wild register address compare enable register WREN Wild register data test setup register WROR Wild register data setup register WRDR Wild register addr...

Page 236: ... enable register WREN enables the wild register function for each wild register data setup register WRDR Moreover the wild register data test setup register WROR enables the normal read function for each wild register data setup register WRDR Control circuit block This circuit compares the actual address data with addresses set in the wild register address setup registers WRDR and if the values ma...

Page 237: ...setup registers WRAR0 to WRAR2 Address bit15 bit8 Initial value 0F80H 0F81H WRAR0 RA15 RA8 00000000B 0F83H 0F84H WRAR1 R W R W R W R W R W R W R W R W bit7 bit0 Initial value 0F86H 0F87H WRAR2 RA7 RA0 00000000B R W R W R W R W R W R W R W R W Wild register address compare enable register WREN Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 0076H WREN Reserved Reserved Reserved EN2 EN...

Page 238: ...egister WRDR has its corresponding wild register number Table 15 3 1 Wild Register Numbers Corresponding to Wild Register Address Setup Registers and Wild Register Data Setup Registers Wild register number Wild register address setup register WRAR Wild register data setup register WRDR 0 WRAR0 WRDR0 1 WRAR1 WRDR1 2 WRAR2 WRDR2 ...

Page 239: ...W R W WRDR2 Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 0F88H RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 00000000B R W R W R W R W R W R W R W R W R W Readable writable Read value is the same as write value Table 15 3 2 Functional Description of Each Bit of Wild Register Data Setup Resister WRDR Bit name Function bit7 to bit0 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 Wild register data setup bits The...

Page 240: ...W R W R W R W R W R W Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 0F84H RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 00000000B R W R W R W R W R W R W R W R W WRAR2 Address bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 Initial value 0F86H RA15 RA14 RA13 RA12 RA11 RA10 RA9 RA8 00000000B R W R W R W R W R W R W R W R W Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 0F87H RA7 RA6 ...

Page 241: ...eserved bit Write value is 0 read value is 0 R W Readable writable Read value is the same as write value Not used Table 15 3 4 Functional Description of Wild Register Address Compare Enable Register WREN Bit name Function bit7 bit6 Unused bits These bits are not used The read value is 0 Write has no effect on the operation bit5 to bit3 Reserved bits These bits are reserved The read value is 0 Alwa...

Page 242: ...Readable writable Read value is the same as write value Not used Table 15 3 5 Functional Description of Wild Register Data Test Setup Register WROR Bit name Function bit7 bit6 Unused bits These bits are not used The read value is 0 Write has no effect on operation bit5 to bit3 Reserved bits These bits are reserved The read value is 0 Always set 0 bit2 to bit0 DRR2 DRR1 DRR0 Wild register data test...

Page 243: ...his address cannot be patched Table 15 4 1 Register Setup Procedure for Wild Register Operating step Operation Example operation 1 Read replacement data from outside through its specific communication method Set the built in ROM code to be modified is in the address F011H and the data to be modified to B5H Three built in ROM codes can be modified 2 Write the replacement address into the wild regis...

Page 244: ...tion Example Shown below is a typical hardware connection example applied when using the wild register function Hardware Connection Example Figure 15 5 1 Typical Hardware Connection Example E2 PROM Stores correction program SO SI SCK SI SO SCK MB95170J series ...

Page 245: ...7 Operating Description of Interval Timer Function One shot Mode 16 8 Operating Description of Interval Timer Function Continuous Mode 16 9 Operating Description of Interval Timer Function Free run Mode 16 10 Operating Description of PWM Timer Function Fixed cycle mode 16 11 Operating Description of PWM Timer Function Variable cycle Mode 16 12 Operating Description of PWC Timer Function 16 13 Oper...

Page 246: ...00H again The timer output a square wave as a result of this repeated operation Interval Timer Function Free run Mode When the interval timer function free run mode is selected the counter starts counting from 00H When the counter value matches the register setting value the timer output is inverted and the interrupt request occurs When the counter continues to count until reaching FFH it restarts...

Page 247: ... When the input capture function is selected the counter value is stored in a register upon detection of an edge for an external input signal This function is available in either free run mode or clear mode for count operation In the clear mode the counter starts counting from 00H and transfers its value to a register to generate an interrupt upon detection of an edge In this case the counter cont...

Page 248: ...it composite timer 00 01 data register x 2 channels T00DR T01DR 8 16 bit composite timer 00 01 control status register 0 x 2 channels T00CR0 T01CR0 8 16 bit composite timer 00 01 control status register 1 x 2 channels T00CR1 T01CR1 8 16 bit composite timer 00 01 timer mode control register TMCR0 Output controller x 2 channels Control logic x 2 channels Count clock selector x 2 channels Edge detect...

Page 249: ...during interval timer or PWM timer operation and to read the count value during PWC timer or input capture operation 8 bit counter 8 bit comparator 8 bit data register Count clock selector Count clock selector Edge detector Output controller 8 bit counter 8 bit comparator 8 bit data register Output controller Control logics Control logics IFE C2 C1 C0 F3 F2 F1 F0 STA HO IE IR BF IF SO OE Timer 00 ...

Page 250: ...logic The control logic controls timer operation Count clock selector The selector selects the counter operation clock signal from among prescaler outputs machine clock divided signal and timebase timer output Edge detector The edge detector selects the edge of an external input signal to be used as an event for PWC timer operation or input capture operation Noise filter This filter serves as a no...

Page 251: ...imer Table 16 3 1 8 16 bit Composite Timer Channels and Corresponding External Pins Channel Pin name Pin function 0 TO00 Timer 00 output TO01 Timer 01 output EC0 Timer 00 input and timer 01 input 1 TO10 Timer 10 output TO11 Timer 11 output EC1 Timer 10 input and timer 11 input Table 16 3 2 8 16 bit Composite Timer Channels and Corresponding Registers Channel Register name Registers 0 T00CR0 Timer ...

Page 252: ...ins indeterminate during 16 bit operation when the PWM timer function variable cycle mode or input capture function has been selected enabling output EC0 pins The EC0 pin is connected to the EC00 and EC01 internal pins EC00 internal pin This pin serves as the external count clock input pin for timer 00 when the interval timer or PWM timer function has been selected or as the signal input pin for t...

Page 253: ...2 bit0 bit0 Initial value 0036H T01CR1 STA HO IE IR BF IF SO OE 00000000B 0037H T00CR1 R W R W R W R RM1 W R WX R RM1 W R W R W 8 16 bit composite timer 00 01 data register T00DR T01DR Address bit7 bit6 bit5 bit4 bit3 bit2 bit0 bit0 Initial value 0F94H T01DR TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDR0 00000000B 0F95H T00DR R W R W R W R W R W R W R W R W 8 16 bit composite timer 00 01 timer mode contr...

Page 254: ...eadable writable Read value is the same as write value R Read only Initial value F3 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 C2 C1 C0 Count clock select bits 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 External clock Interval timer one shot mode Interval timer continuous mode Interval timer free run mode PWM timer fixed cycle mode PWM timer variable cycle...

Page 255: ...ted by the prescaler Refer to 6 12 Operating Explanation of Prescaler Write access to these bits is nullified during timer operation T00CR1 T01CR1 STA 1 The clock selection of T01CR0 timer 01 is nullified during 16 bit operation These bits cannot be set to 111B when the PWC or input capture function is used An attempt to write 111B with the PWC or input capture function in use resets the bits to 0...

Page 256: ...nctional Description of Each Bit of 8 16 bit Composite Timer 00 01 Control Status Register 0 T00CR0 T01CR0 2 2 Bit name Function F3 F2 F1 F0 Timer operation mode select bits 0 0 0 0 Interval timer one shot mode 0 0 0 1 Interval timer continuous mode 0 0 1 0 Interval timer free run mode 0 0 1 1 PWM timer fixed cycle mode 0 1 0 0 PWM timer variable cycle mode 0 1 0 1 PWC timer H pulse rising to fall...

Page 257: ...243 CHAPTER 16 8 16 BIT COMPOSITE TIMER ...

Page 258: ...RM1 W R WX R RM1 W R W R W Initial value IE Interrupt enable bit 0 Interrupt disabled 1 Interrupt enabled HO Timer pause bit 0 Timer operable 1 Timer paused STA Timer operation enable bit 0 Timer stopped 1 Timer operable Read Write Flag clear No effect on operation R W Readable writable Read value is the same as write value R RM1 W Readable writable Read value is different from write value 1 is re...

Page 259: ...variable cycle mode has been selected T00CR0 T01CR0 F3 F2 F1 F0 0100B the HO bit can be used to suspend or resume timer operation from within either the T00CR1 timer 00 or T01CR1 timer 01 register In this case the HO bit in the other register is set to the same value automatically During 16 bit operation TMCR0 MD 1 use the HO bit in the T00CR1 timer 00 register to suspend or resume timer operation...

Page 260: ...alue or a counter overflow The bit is set to 1 when the 8 16 bit composite timer 00 01 data register T00DR T01DR value matches the count value during interval timer function both one shot and continuous mode or PWM timer function variable cycle mode The bit is set to 1 when a counter overflow occurs during PWC or input capture function This bit always returns 1 to a read modify write instruction W...

Page 261: ...247 CHAPTER 16 8 16 BIT COMPOSITE TIMER ...

Page 262: ...put bit 1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value TO1 TO0 IIS MOD FE11 FE10 FE01 FE00 00000000B R WX R WX R W R W R W R W R W R W Initial value R W Readable writable Read value is the same as write value R RM1 W Readable writable Read value is different from write value 1 is read by read modfy write instruction R WX Read only Readable writting has no effect on operation FE01 FE00 Tim...

Page 263: ...PWC timer function this bit holds the last value When the timer stops operation in PWM timer function fixed cycle mode this bit holds the last value When the timer operation mode select bit T00CR0 T01CR0 F3 F2 F1 F0 is changed with the timer being stopped the bit indicates the last value of timer operation if the same timer operation has ever been performed or otherwise contains 0 bit5 IIS Timer 0...

Page 264: ...llified during timer operation T00CR1 STA 1 The settings of these bits have no effect on operation when the interval timer or PWM timer function has been selected filter function does not operate Table 16 5 3 Functional Description of Each Bit of 8 16 bit Composite Timer 00 01 Timer Mode Control Register TMCR0 2 2 Bit name Function FE01 FE00 Timer 00 filter function select bits 0 0 No filtering 0 ...

Page 265: ...d from this register An attempt to write 00H to this register is disabled in interval timer function In 16 bit operation set the upper data to T01DR and lower data to T00DR And write and read T01DR and T00DR in this order PWM timer functions fixed cycle The 8 16 bit composite timer 00 01 data register T00DR T01DR is used to set H pulse width time When the timer starts operation T00CR1 T01CR1 STA 1...

Page 266: ...1 data register is not performed with the BF bit containing 1 As the exception when the H pulse and cycle measurement T00CR0 T01CR0 F3 F2 F1 F0 1001B is selected the H pulse measurement result is transferred to the 8 16 bit composite timer 00 01 data register with the BF bit set to 1 but the cycle measurement result is not transferred to the 8 16 bit composite timer 00 01 data register with the BF...

Page 267: ...R value into the internal read buffer Read from T00DR Read from the internal read buffer Write to T01DR Write to the internal write buffer Write to T00DR Write access to the register also involves storing the value of the internal write buffer into T01DR The following diagram illustrates how T00DR and T01DR registers read from and written to during 16 bit operation T00DR register T01DR register Re...

Page 268: ... in PWC timer function or input capture function Completion of measurement in PWC timer function or edge detection in input capture function Interrupt flag T00CR1 IF T00CR1 IF T00CR1 IR Interrupt enable T00CR1 IE and T00CR0 IFE T00CR1 IE and T00CR0 IFE T00CR1 IE Table 16 6 2 Timer 01 Interrupt Item Description Interrupt generating condition Comparison match in interval timer function or PWM timer ...

Page 269: ... in APPENDIX B Table of Interrupt Causes Table 16 6 3 Registers and Vector Tables Related to Interrupts of 8 16 bit Composite Timer Interrupt source Interrupt request No Interrupt level setup register Vector table address Register Setting bit Upper Lower Timer 00 IRQ5 ILR1 L05 FFF0H FFF1H Timer 01 IRQ6 ILR1 L06 FFEEH FFEFH Timer 10 IRQ22 ILR5 L22 FFCEH FFCFH Timer 11 IRQ14 ILR3 L14 FFDEH FFDFH ...

Page 270: ... value of the 8 16 bit composite timer 00 01 data register T00DR T01DR the timer output TMCR0 TO0 TO1 is inverted the interrupt flag T00CR1 T01CR1 IF is set to 1 and the start bit T00CR0 T00CR1 STA is set to 0 and then the count operation stops The value of the 8 16 bit composite timer 00 01 data register T00DR T01DR is transferred to the temporary storage latch comparison data storage latch in th...

Page 271: ...gram Time IF bit STA bit T00 01DR value FFH Timer output pin Automatically cleared Reactivated Inverted For initial value 1 on activation If the T00 01DR data register value is modified during operation the new value is used from the next active cycle Automatically cleared Reactivated Reactivated with output initial value unchanged 0 T00 01DR value modified FFH 80H ...

Page 272: ...r T00DR T01DR the timer output bit TMCR0 TO0 TO1 is inverted the interrupt flag T00CR1 T01CR1 IF is set to 1 and the counter continues to count by restarting at 00H The timer outputs a square wave as a result of this continuous operation The value of the 8 16 bit composite timer 00 01 data register T00DR T01DR is transferred to the temporary storage latch comparison data storage latch in the compa...

Page 273: ...F bit STA bit Counter clear 2 Timer output pin 1 If the T00 01DR data register value is modified during operation the new value is used from the next active cycle E0H Compare value E0H Activated Matched Matched Matched Matched Matched 2 The counter is cleared and the data register settings are loaded into the comparison data latch when a match is detected at each point during activation T00 01DR v...

Page 274: ...e timer output bit TMCR0 TO0 TO1 is inverted and the interrupt flag T00CR1 T01CR1 IF is set to 1 The counter continues to count and when the count value reaches FFH it restarts counting at 00H to continue The timer outputs a square wave as a result of this continuous operation The value of the 8 16 bit composite timer 00 01 data register T00DR T01DR is transferred to the temporary storage latch co...

Page 275: ...d by program Time IF bit STA bit Counter value match Timer output pin E0H E0H Activated Matched Matched Matched The counter is not cleared and the data register settings are not reloaded into the comparison data latch when a match is detected at each point during activation Matched Although the T00 01DR value is modified it is not updated into the comparison latch ...

Page 276: ...t composite timer 00 01 data register T00DR T01DR This function has no effect on the interrupt flag T00CR1 T01CR1 IF As each cycle always starts with H pulse output the timer output initial value setting bit T00CR1 T01CR1 SO is meaningless The value of the 8 16 bit composite timer 00 01 data register T00DR T01DR is transferred to the temporary storage latch comparison data storage latch in the com...

Page 277: ...ounter value H L H L H L 00H Counter value Counter value PWM waveform PWM waveform PWM waveform T00 01DR register value 80H duty ratio 50 T00 01DR register value FFH duty ratio 99 6 FFH00H FFH00H 80H One count width Note When the PWM function has been selected the timer output pin holds the level used when the counter stops T00 01CR0 STA 0 FFH00H 00H 00H ...

Page 278: ...he timer initial value setting bit T00CR1 T01CR1 SO is meaningless The interrupt flag T00CR1 T01CR1 IF is set when each 8 bit counter matches the value in the corresponding 8 16 bit composite timer 00 01 data register T00DR T01DR The 8 16 bit composite timer 00 01 data register value is transferred to the temporary storage latch comparison data storage latch in the comparator either when the count...

Page 279: ...01DR register value 80H duty ratio 0 FFH00H 80H00H 00H 80H00H 80H00H 00H 80H00H Counter timer 01 value Counter timer 00 value Counter timer 01 value 00H 00H 00H 80H00H 00H 80H00H 40H 40H Counter timer 00 value Counter timer 01 value 00H 00H One count width timer 00 value timer 01 value T00DR register value 40H and T01DR register value 80H duty ratio 50 T00DR register value 00H and T01DR register v...

Page 280: ...full flag set to 1 Even when the next edge is detected at this time the next measurement result is lost as the count value is not transferred to the 8 16 bit composite timer 00 01 data register As the exception when the H pulse and cycle measurement T00CR0 T01CR0 F3 F2 F1 F0 1001B is selected the H pulse measurement result is transferred to the 8 16 bit composite timer 00 01 data register with the...

Page 281: ...st value The value of the 8 16 bit composite timer 00 01 data register T00DR T01DR must be nullified if an interrupt occurs before the timer is activated before 1 is written to the STA bit Figure 16 12 2 Operating Diagram of PWC Timer Example of H pulse Width Measurement Pulse input Input waveform to PWC pin Counter value FFH STA bit IR bit BF bit H width Counter operation Time Cleared by program ...

Page 282: ...e interrupt flag T00CR1 T01CR1 IR is set to 1 and the counter continues to count by restarting at 00H When the edge is detected in free run mode the counter value is transferred to the 8 16 bit composite timer 00 01 data register T00DR T01DR and the interrupt flag T00CR1 T01CR1 IR is set to 1 In this case the counter continues to count without being cleared This function has no effect on the buffe...

Page 283: ... Operating Diagram of Input Capture Function FFH BFH 7FH 9FH 3FH 3FH 9FH Counter free run mode Counter clear mode BFH 7FH Capture value in T00 01DR Falling edge of capture Rising edge of capture External input Falling edge of capture Rising edge of capture ...

Page 284: ...l from the external input pin EC00 EC01 H pulse noise L pulse noise or H L pulse noise elimination can be selected depending on the register setting TMCR0 F11 F10 F01 F00 The maximum pulse width from which to eliminate noise is three machine clock cycles When the filter function is active the signal input is subject to a delay of four machine clock cycles Figure 16 14 1 Operation of Noise Filter S...

Page 285: ...p mode or watch mode is canceled by an interrupt the counter resumes operation with the last value held So the first interval time and external clock count are incorrect After releasing from stop mode or watch mode be sure to initialize the counter value Figure 16 15 1 Operations of Counter in Standby Mode or in Pause Not Serving as PWM Timer Counter value FFH 80H 00H T00 01DR data register value ...

Page 286: ...ime STA bit PWM timer output pin FFH SLP bit STBC register STP bit STBC register Sleep mode The PWM timer output maintains the value held before it enters the stop mode HO bit Wake up from sleep mode by interrupt Delay of oscillation stabilization wait time Maintains the level prior to stop Wake up from stop mode by external interrupt Maintains the level prior to hold ...

Page 287: ...n mode select bits T00CR0 T01CR0 F3 F2 F1 F0 the timer operation must be stopped T00CR1 T01CR1 STA 0 before clearing the interrupt flag T00CR1 T01CR1 IF IR interrupt enable bits T00CR1 T01CR1 IE T00CR0 T01CR0 IFE and buffer full flag T00CR1 T01CR1 BF When the PWC or input capture function has been selected an interrupt may occur even before the timer is activated STA 0 Therefore nullify the value ...

Page 288: ...274 CHAPTER 16 8 16 BIT COMPOSITE TIMER ...

Page 289: ...mer 17 2 Configuration of 16 bit PPG Timer 17 3 Channels of 16 bit PPG Timer 17 4 Pins of 16 bit PPG Timer 17 5 Registers of 16 bit PPG Timer 17 6 Interrupts of 16 bit PPG Timer 17 7 Explanation of 16 bit PPG Timer Operations and Setup Procedure Example 17 8 Precautions when Using 16 bit PPG Timer 17 9 Sample Programs for 16 bit PPG Timer ...

Page 290: ...ormal polarity Inverted polarity Output waveform PWM waveform Normal polarity Inverted polarity One shot waveform Normal polarity Inverted polarity The count operation clock can be selected from eight different clock sources MCLK 1 MCLK 2 MCLK 4 MCLK 8 MCLK 16 MCLK 32 FCH 27 or FCH 28 MCLK Machine clock FCH Clock Interrupt can be selectively triggered by the following four conditions Occurrence of...

Page 291: ...0 Internal data bus MCLK 2 STOP Edge detection STGR CNTE RTRG POEN 7 8 1 0 16 bit PPG cycle setting buffer register upper 8 bits 16 bit PPG cycle setting buffer register lower 8 bits 16 bit PPG cycle setting buffer register upper 8 bits buffer 16 bit PPG duty setting buffer register lower 8 bits 16 bit PPG duty setting buffer register upper 8 bits 16 bit PPG duty setting buffer register for lower ...

Page 292: ...t TRG4 Trigger 4 input 5 PPG5 PPG5 output TRG5 Trigger 5 input 6 PPG6 PPG6 output TRG6 Trigger 6 input 7 PPG7 PPG7 output TRG7 Trigger 7 input Table 17 3 2 Registers of 16 bit PPG Timer Channel Register name Corresponding register name in this manual i i 0 7 PDCRHi 16 bit PPG down counter register upper of ch i PDCRLi 16 bit PPG down counter register lower of ch i PCSRHi 16 bit PPG cycle setting b...

Page 293: ...e other channels are the same as it The pins related to the 16 bit PPG timer are namely the PPG0 pin PPG0 pin Each pin serves as a general purpose I O port as well as a 16 bit PPG timer output PPG0 A PPG waveform is outputted to these pins The PPG waveform can be outputted by using the 16 bit PPG status control register to enable output PCNTL0 POEN 1 TRG0 pin Used to start 16 bit PPG timer by hard...

Page 294: ... 0 Peripheral function output Peripheral function output enable Peripheral function input enable Peripheral function input Pin Stop Watch SPL 1 Internal bus In bit operation instruction Pull up ILSR2 read ILSR2 write ILSR2 Hysteresis Automotive Only P12 is selectable PDR read PDR write PDR DDR read DDR write DDR 0 1 1 0 Peripheral function output Peripheral function output enable Pin Stop Watch SP...

Page 295: ... output Peripheral function output enable Peripheral function input Pin Stop Watch SPL 1 Internal bus In bit operation instruction Pull up Selectalbe only P94 and P95 ILSR2 read ILSR2 write ILSR2 Hysteresis Automotive PDR read PDR write PDR DDR read DDR write DDR 0 1 Pin Stop Watch SPL 1 Internal bus Peripheral function input enable Peripheral function input In bit operation instruction ILSR3 read...

Page 296: ...X R WX 0FB7H PDCRL2 0FA5H PDCRL3 0F2BH PDCRL4 0F31H PDCRL5 0F37H PDCRL6 0F25H PDCRL7 16 bit PPG cycle setting buffer register upper PCSRH Address bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 Initial value 0FACH PCSRH0 CS15 CS14 CS13 CS12 CS11 CS10 CS09 CS08 11111111B 0FB2H PCSRH1 R W R W R W R W R W R W R W R W 0FB8H PCSRH2 0FA6H PCSRH3 0F2CH PCSRH4 0F32H PCSRH5 0F38H PCSRH6 0F26H PCSRH7 16 bit P...

Page 297: ...R W R W 0FBBH PDUTL2 0FA9H PDUTL3 0F2FH PDUTL4 0F35H PDUTL5 0F3BH PDUTL6 0F29H PDUTL7 16 bit PPG status control register upper PCNTH Address 15 14 13 12 11 10 9 8 Initial value 0042H PCNTH0 CNTE STRG MDSE RTRG CKS2 CKS1 CKS0 PGMS 00000000B 0044H PCNTH1 R W R0 W R W R W R W R W R W R W 0046H PCNTH2 0050H PCNTH3 003AH PCNTH4 003CH PCNTH5 003EH PCNTH6 0040H PCNTH7 16 bit PPG status control register l...

Page 298: ...nd read PDCRH0 first and PDCRL0 second reading PDCRH0 automatically copies the lower 8 bits of the down counter to PDCRL0 These registers are read only and writing has no effect on the operation Note If you use the MOV instruction and read PDCRL0 before PDCRH0 PDCRL0 will return the value from the previous valid read operation Therefore the value of the 16 bit down counter will not be read correct...

Page 299: ...the previous valid PCSRH0 PCSRL0 value will be loaded to the down counter If the PCSRH0 PCSRL0 value is modified during counting the modified value will become effective from the next load of the down counter Do not set PCSRH0 and PCSRL0 to 00H or PCSRH0 to 00H and PCSRL0 to 01H Note If the down counter load occurs after the MOV instruction is used to write data to PCSRL0 before PCSRH0 the previou...

Page 300: ...tween the value of the 16 bit PPG duty setting registers and output pulse is as follows When the same value is set in both the 16 bit PPG cycle setting buffer registers and duty setting registers the H level will always be outputted if normal polarity is set or the L level will always be outputted if inverted polarity is set When the duty setting registers are set to 00 the L level will always be ...

Page 301: ...287 CHAPTER 17 16 BIT PPG TIMER ...

Page 302: ...tput mask 0 1 CKS2 CKS1 CKS0 0 0 0 MCLK 1 MCLK 2 MCLK 4 MCLK 8 MCLK 16 MCLK 32 FCH 27 FCH 28 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 RTRG 0 1 MDSE 0 PWM mode Mode select bit 1 STRG Software trigger bit No effect on operation Generates software trigger Write Read 0 Always reads 0 1 CNTE 0 1 R W Readable writable Read value is the same as write value Initial value Counter clock select bit MCLK Mac...

Page 303: ...This bit is used to enable or disable the software retrigger function of the PPG during operation When the bit is set to 0 the software retrigger function is disabled When the bit is set to 1 the software retrigger function is enabled bit1 bit2 bit3 CKS2 0 Count clock select bits These bits select the operating clock for the 16 bit PPG timer The count clock signal is generated by the prescaler Ref...

Page 304: ...M mode Mode select bit 1 STRG Software trigger bit No effect on operation Generates software trigger Write Read 0 Always reads 0 1 CNTE 0 1 R W Readable writable Read value is the same as write value Initial value Counter clock select bit MCLK Machine clock Software retrigger enable bit Disables software retrigger Enables software retrigger One shot mode Timer enable bit Stops PPG timer Enables PP...

Page 305: ...when a PPG interrupt occurs When the bit is set to 0 clears the bit When the bit is set to 1 has no effect on operation 1 is always read in read modify write operations bit3 bit2 IRS1 IRS0 Interrupt type select bits These bits select the interrupt type for the PPG timer bit1 POEN Output enable bit This bit enables or disables output from the PPG output pin When the bit is set to 0 the pin serves a...

Page 306: ...PENDIX B Table of Interrupt Causes shows the interrupt request numbers and vector tables for all peripheral functions Table 17 6 1 Interrupt Control Bits and Interrupt Sources of 16 bit PPG Timer Item Description Interrupt flag bit PCNTL0 IRQF Interrupt request enable bit PCNTL0 IREN Interrupt type select bits PCNTL0 IRS1 0 Interrupt sources PCNTL0 IRS1 0 00 Hardware trigger by TRG Pin input of 16...

Page 307: ...ut changes back to L when the H was output until the value of duty setting The output levels will be reversed if OSEL is set to 1 When the retrigger function is disabled RTRG 0 software triggers STRG 1 are ignored during the operation of the down counter When the down counter is not running the maximum time between a valid trigger input occurring and the down counter starting is as follows Softwar...

Page 308: ... 1 n T ns 2 m T ns PPG 1 2 Normal polarity Inverted polarity Time 16 bit down counter value Software trigger n PDUTH0 PDUTL0 register value m PCSRH0 PCSRL0 register value T Count clock cycle Rising edge detected Trigger ignored m n 0 1 n T ns 2 m T ns PPG PPG 1 2 Normal polarity Inverted polarity Time Counter value Software trigger Rising edge detected Restarted by trigger n PDUTH0 PDUTL0 register...

Page 309: ...e output levels will be reversed if OSEL is set to 1 Invalidating the retrigger RTRG of PCNTH0 register bit 4 0 Figure 17 7 3 When Retrigger Is Invalid in One shot Mode Validating the retrigger RTRG of PCNTH0 register bit 4 1 Figure 17 7 4 When Retrigger Is Valid in One shot Mode m n 0 Trigger ignored 1 n T ns 2 m T ns PPG PPG 1 2 Normal polarity Inverted polarity Time Counter value Software trigg...

Page 310: ...been selected Figure 17 7 5 Hardware Trigger in PWM Mode Setup Procedure Example The 16 bit PPG timer is set up in the following procedure Initial setup 1 Set the interrupt level ILR5 2 Enable the hardware trigger and interrupts select the interrupt type and enable output PCNTL 3 Select the count clock and the mode and enable timer operation PCNTH 4 Set the cycle PCSR 5 Set the duty PDUT 6 Start t...

Page 311: ...e TRG pin setting may change and cause the device to malfunction Therefore disable the timer enable bit PCNTH0 CNTE 0 or disable the hardware trigger enable bit PCNTL0 EGS1 EGS0 00 When the cycle and duty are set to the same value an interrupt is generated only once by duty match Moreover if the duty is set to a value greater than the value of the period no interrupt will be generated by duty matc...

Page 312: ...erating clock select bits PCNTH0 CKS2 CKS1 CKS0 are used to select the clock How to enable disable the PPG output pin The output enable bit PCNTL0 POEN is used How to enable stop PPG operation The timer enable bit PCNTH0 CNTE is used Enable PPG operation before starting the PPG Operation mode Operation mode select bit MDSE PWM mode Set the bit to 0 One shot mode Set the bit to 1 What to be control...

Page 313: ... bit PCNTL0 OSEL is used What to be controlled Software trigger bit STGR When starting PPG operation by software Set the bit to 1 What to be controlled Retrigger enable bit RTRG When enabling retrigger function Set the bit to 1 When disabling retrigger function Set the bit to 0 What to be controlled Hardware trigger enable bit EGS0 When starting operation on rising edge Set the bit to 1 When stopp...

Page 314: ...bit OSEL When setting output to H level Set the bit to 1 Set the bit to 1 When setting output to L level Set the bit to 1 Set the bit to 0 Interrupt source Interrupt select bits IRS1 IRS0 Trigger by TRG input software trigger or retrigger Set the bits to 00 Counter borrow Set the bits to 01 Rising edge of PPG output in normal polarity or falling edge of PPG output in inverted polarity Set the bits...

Page 315: ... IREN is used to enable interrupts The interrupt request flag PCNTL0 IRQF is used to clear interrupt requests What to be controlled Interrupt request enable bit IREN When disabling interrupt request Set the bit to 0 When enabling interrupt request Set the bit to 1 What to be controlled Interrupt request flag IRQF When clearing interrupt request Write 0 to the bit ...

Page 316: ...302 CHAPTER 17 16 BIT PPG TIMER ...

Page 317: ...8 2 Configuration of External Interrupt Circuit 18 3 Channels of External Interrupt Circuit 18 4 Registers of External Interrupt Circuit 18 5 Interrupts of External Interrupt Circuit 18 6 Explanation of External Interrupt Circuit Operations and Setup Procedure Example 18 7 Precautions when Using External Interrupt Circuit 18 8 Sample Programs for External Interrupt Circuit ...

Page 318: ...ternal interrupt pin and generates interrupt requests to the CPU Functions of External Interrupt Circuit The external interrupt circuit has the functions to detect any edge of a signal that is inputted to an external interrupt pin and generate an interrupt request to the CPU This interrupt allows the unit to recover from a standby mode and return to its normal operation ...

Page 319: ...ernal interrupt circuit pin INT matches the polarity of the edge selected in the interrupt control register EIC the corresponding external interrupt request flag bit EIR is set to 1 External interrupt control register EIC This register is used to select the valid edge enable or disable interrupt requests check for interrupt requests etc EIR1 SL11 SL10 EIE1 EIR0 SL01 SL00 EIE0 External interrupt co...

Page 320: ...ut pin INT00 INT13 The state of pins can be read from the port data register PDR whenever input port is set as a pin function However the value of PDR is read when read modify write instruction is used Table 18 3 1 Pins of External Interrupt Circuit Unit Pin name Pin function 0 INT00 External interrupt input ch 0 INT01 External interrupt input ch 1 1 INT02 External interrupt input ch 2 INT03 Exter...

Page 321: ...B R RM1 W R W R W R W R RM1 W R W R W R W Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 0049H EIC10 EIR1 SL11 SL10 EIE1 EIR0 SL01 SL00 EIE0 00000000B R RM1 W R W R W R W R RM1 W R W R W R W Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 004AH EIC20 EIR1 SL11 SL10 EIE1 EIR0 SL01 SL00 EIE0 00000000B R RM1 W R W R W R W R RM1 W R W R W R W Address bit7 bit6 bit5 bit4 bi...

Page 322: ...sing edge 0 Both edges External interrupt request flag bit 0 Read Write Specified edge not inputted EIR0 Clears this bit 0 Specified edge inputted 1 No change no effect on others Falling edge 1 0 1 1 1 SL00 Interrupt request enable bit 1 Disables output of interrupt request Enables output of interrupt request EIE1 0 1 Edge polarity select bits 1 No edge detection SL11 0 Rising edge 0 Both edges Ex...

Page 323: ...t the pin as an input The status of the external interrupt pin can be read directly from the port data register regardless of the status of the interrupt request enable bit bit3 EIR0 External interrupt request flag bit 0 This flag is set to 1 when the edge selected by the edge polarity select bits SL01 SL00 is inputted to the external interrupt pin INT0 When this bit and the interrupt request enab...

Page 324: ...abled EIC EIE0 EIE1 1 Write 0 to the corresponding external interrupt request flag big to clear the interrupt request in the interrupt process routine Registers and Vector Table Related to Interrupts of External Interrupt Circuit ch Channel APPENDIX B Table of Interrupt Causes describes the interrupt request numbers and vector tables for all peripheral functions Table 18 5 1 Registers and Vector T...

Page 325: ...interrupt to recover from a standby mode When setting the edge polarity select bit SL set the interrupt request enable bit EIE to 0 to prevent the interrupt request from being generated accidentally Also clear the interrupt request flag bit EIR to 0 after changing the edge polarity Figure 18 6 1 shows the operation for setting the INT0 pin as an external interrupt input Figure 18 6 1 Operation of ...

Page 326: ...Clear the interrupt request flag EIC EIR0 0 2 Process any interrupt Note The external interrupt input is also used as an I O port Therefore when it is used as the external interrupt input the corresponding bit in the port direction register DDR must be set to 0 input ...

Page 327: ...e interrupt request enable bit EIE to 0 disabling interrupt requests when setting the edge polarity select bit SL Also clear the external interrupt request flag bit EIR to 0 after setting the edge polarity The operation cannot recover from the interrupt processing routine if the external interrupt request flag bit is 1 and the interrupt request enable bit is enabled Always clear the external inter...

Page 328: ...s Select 01 Detecting falling edges Select 10 Detecting both edges Select 11 Operation Direction bit Pxx to Pxx Setting Using INT00 pin for external interrupt DDR0 P00 Set the register to 0 Using INT01 pin for external interrupt DDR0 P01 Set the register to 0 Using INT02 pin for external interrupt DDR0 P02 Set the register to 0 Using INT03 pin for external interrupt DDR0 P03 Set the register to 0 ...

Page 329: ...FFF6H ch 3 Interrupt level register ILR0 Address 00079H 3 Address 0FFF4H ch 4 Interrupt level register ILR0 Address 00079H 0 Address 0FFFAH ch 5 Interrupt level register ILR0 Address 00079H 1 Address 0FFF8H ch 6 Interrupt level register ILR0 Address 00079H 2 Address 0FFF6H ch 7 Interrupt level register ILR0 Address 00079H 3 Address 0FFF4H ch 8 Interrupt level register ILR5 Address 0007EH 21 Addres...

Page 330: ...the interrupt enable bit EIC00 EIE0 or 1 Interrupt requests are cleared by the interrupt request bit EIC00 EIR0 or 1 What to be controlled Interrupt enable bit EIE0 or 1 When disabling interrupt request Set the bit to 0 When enabling interrupt request Set the bit to 1 What to be controlled Interrupt request bit EIR0 or 1 When clearing interrupt request Write 0 ...

Page 331: ...n circuit 19 1 Overview of Interrupt Pin Selection Circuit 19 2 Configuration of Interrupt Pin Selection Circuit 19 3 Pins of Interrupt Pin Selection Circuit 19 4 Registers of Interrupt Pin Selection Circuit 19 5 Operating Description of Interrupt Pin Selection Circuit 19 6 Precautions when Using Interrupt Pin Selection Circuit ...

Page 332: ...t Pin Selection Circuit The interrupt pin selection circuit is used to select interrupt input pins from amongst various peripheral inputs TRG0 ADTG UCK0 UI0 EC0 SCK SI INT00 The input signal from each peripheral function pin is selected by this circuit and the signal is used as the INT00 channel 0 input of external interrupt This enables the input signals to the peripheral function pins to also se...

Page 333: ...This register is used to determine which of the available peripheral input pins should be outputted to the interrupt circuit and which interrupt pins they should serve as Selection circuit This circuit outputs the input from the pin selected by the WICR register to the INT00 input of the external interrupt circuit channel 0 Pin INT01 External interrupt circuit INT01 INT00 Unit 0 Interrupt pin sele...

Page 334: ...sly Table 19 3 1 lists the correlation between the peripheral functions and peripheral input pins Table 19 3 1 Correlation Between Peripheral Functions and Peripheral Input Pins Peripheral input pin name Peripheral functions name INT00 Interrupt pin selection circuit TRG0 ADTG Interrupt pin selection circuit 16 bit PPG timer trigger input A D converter trigger input UCK0 Interrupt pin selection ci...

Page 335: ... Selection Circuit Figure 19 4 1 Registers Related to Interrupt Pin Selection Circuit Interrupt pin control selection circuit register WICR Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 0FEFH INT00 SI SCK EC0 UI0 UCK0 TRG0 01000000B R0 WX R W R W R W R W R W R W R W R0 WX Undefined bit Read value is 0 writing has no effect on operation R W Readable writable Read value is the same a...

Page 336: ...ut pin Selects TRG0 as interrupt input pin 0 UCK0 1 UCK0 interrupt pin selection bit Deselects UCK0 as interrupt input pin Selects UCK0 as interrupt input pin 0 UI0 1 UI0 interrupt pin selection bit Deselects UI0 as interrupt input pin Selects UI0 as interrupt input pin 0 EC0 1 EC0 interrupt pin selection bit Deselects EC0 as interrupt input pin Selects EC0 as interrupt input pin 0 SCK 1 SCK inter...

Page 337: ...s bit is used to determine whether to select the SCK pin as an interrupt input pin Writing 0 to the bit deselects the SCK pin as an interrupt input pin and the circuit treats the SCK pin input as being fixed at 0 Writing 1 to the bit selects the SCK pin as an interrupt input pin and the circuit passes the SCK pin input to INT00 channel 0 of the external interrupt circuit In this case the input sig...

Page 338: ...ain enabled to perform input so as to accept interrupts even in a standby mode bit1 UCK0 UCK0 interrupt pin select bit This bit is used to determine whether to select the UCK0 pin as an interrupt input pin Writing 0 to the bit deselects the UCK0 pin as an interrupt input pin and the circuit treats the UCK0 pin input as being fixed at 0 Writing 1 to the bit selects the UCK0 pin as an interrupt inpu...

Page 339: ...IC00 register of the external interrupt circuit the operation of the external interrupt circuit is disabled 3 Enable the operation of INT00 of the external interrupt circuit channel 0 Set the SL01 and SL00 bits of the EIC00 register to any value other than 00B in the external interrupt circuit to select the valid edge Also write 1 to the EIE0 bit to enable interrupts 4 The subsequent interrupt ope...

Page 340: ...n WICR interrupt pin selection circuit control register simultaneously and the operation of INT00 channel 0 of the external interrupt circuit is enabled Set the SL01 and SL00 bits of the EIC00 register to any value other than 00B in the external interrupt circuit to select the valid edge Also write 1 to the EIE0 bit to enable interrupts the selected pins will remain enabled to perform input so as ...

Page 341: ...s of UART SIO 20 1 Overview of UART SIO 20 2 Configuration of UART SIO 20 3 Channels of UART SIO 20 4 Pins of UART SIO 20 5 Registers of UART SIO 20 6 Interrupts of UART SIO 20 7 Explanation of UART SIO Operations and Setup Procedure Example 20 8 Sample Programs for UART SIO ...

Page 342: ... full duplex communication The synchronous or asynchronous transfer mode can be selected The optimum baud rate can be selected with the dedicated baud rate generator The data length is variable it can be set to 5 to 8 bits when no parity is used or to 6 to 9 bits when parity is used See Table 20 1 1 The serial data direction endian can be selected The data transfer format is NRZ Non Return to Zero...

Page 343: ...ck input UCK0 Serial data input UI0 Start bit detection Recep tion bit count Parity operation Shift register for reception UART SIO serial input data register UART SIO serial status and data register UART SIO serial mode control registers 1 2 UART SIO serial output data register Shift register for trans mission Transmis sion bit count Parity operation Serial data output UO0 Serial clock output Por...

Page 344: ...n and interrupts and to clear the reception error flag UART SIO serial status and data register SSR0 This register indicates the transmission reception status and error status of UART SIO UART SIO serial input data register RDR0 This register holds the receive data The serial input is converted and then stored in this register UART SIO serial output data register TDR0 This register sets the transm...

Page 345: ...nnel Table 20 3 1 Pins of UART SIO Channel Pin name Pin function 0 UCK0 Clock input output UO0 Data output UI0 Data input Table 20 3 2 Registers of UART SIO Channel Register name Corresponding register Name in this manual 0 SMC10 UART SIO serial mode control register 1 SMC20 UART SIO serial mode control register 2 SSR0 UART SIO serial status and data register TDR0 UART SIO serial output data regis...

Page 346: ... select the external clock set SMC10 CKS 0 When it is to be used as a UART SIO clock input pin disable the clock output SMC20 SCKE 0 and make sure that it is set as input port by the corresponding port direction register At this time be sure to select the external clock set SMC10 CKS 0 UO0 Serial data output pin for UART SIO When the serial data output is enabled SMC20 TXOE 1 it serves as a UART S...

Page 347: ...E TEIE 00100000B R W R W R W R W R W R W R W R W UART SIO serial status and data register SSR0 Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 0058H SSR0 PER OVE FER RDRF TCPL TDRE 00000001B R0 WX R0 WX R WX R WX R WX R WX R RM1 W R WX UART SIO serial output data register TDR0 Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 0059H TDR0 TD7 TD6 TD5 TD4 TD3 TD2 TD1 TD0 XXX...

Page 348: ...smit receive data from MSB side sequentially Serial data direction control bit SBL 0 1 1 bit length 2 bit length Stop bit length control bit PEN 0 1 No parity With parity Parity control bit R W Readable writable Read value is the same as write value Initial value BDS TDP SBL bit7 Address 0056H SMC10 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00000000B Initial value R W PEN CBL1 CKS MD CBL0 R W R W R W R W...

Page 349: ...ls the length of the stop bit in clock asynchronous mode Setting this bit to 0 sets the stop bit length to 1 Setting this bit to 1 sets the stop bit length to 2 Note The setting of this bit is only valid for transmission operation in clock asynchronous mode For receiving operation reception data register full flag is se to 1 after detecting stop bit 1 bit and completing the reception regardless of...

Page 350: ...ption interrupt enable bit 0 1 Clears each error flag No change to this bit no effect on others Reception error flag clear bit RXE bit7 Address 0057H SMC20 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00100000B Initial value TXE TCIE TEIE RIE R W R W SCKE TOEXRERC R W R W R W R1 W R W R W TEIE SCKE TXOE RERC RXE TXE 0 1 Disables transmission data register empty interrupt Enables transmission data register e...

Page 351: ... register Note Setting this bit to 0 initializes reception operation It has no effect on the interrupt flags PER OVE FRE RDRF bit3 TXE Transmissionoperation enable bit Setting the bit to 0 disables the transmission of serial data Setting the bit to 1 enables the transmission of serial data If this bit is set to 0 during transmission the transmission operation will be immediately disabled and initi...

Page 352: ... by read modfy write instruction R WX Read only Readable writting has no effect on operation Initial value PER OVE FER RDRF TCPL R WX R WX bit7 Address 0058H SSR0 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00000001B Initial value R WX R WX R RM1 W OVE 0 1 Overrun error absent Overrun error present Overrun error flag FER 0 1 Framing error absent Framing error present Framing error flag TCPL 0 1 Cleared by ...

Page 353: ...t clears this flag If error detection and clearing by RERC occur at the same time the error flag is set preferentially bit2 RDRF Receive data register full This flag indicates the status of the UART SIO serial input data register The bit is set to 1 when receive data is loaded to the serial input data register The bit is cleared to 0 when data is read from the serial input data register bit1 TCPL ...

Page 354: ...eceived data is set correctly in this register the receive data register full RDRF bit is set to 1 At this time an interrupt occurs if reception interrupt requests have been enabled If an RDRF bit check by the program or using an interruption shows that received data is stored in this register the reading of the content for this register clears the RDRF flag to 0 When the character bit length CBL1...

Page 355: ...er TDR0 the transmission data register empty bit TDRE is set to 0 Upon completion of transfer of transmit data to the transmission shift register the transmission data register empty bit TDRE is set to 1 allowing the next piece of transmit data to be written At this time an interrupt occurs if transmission data register empty interrupts have been enabled Write the next piece of transmit data when ...

Page 356: ...eption Interrupt If the data is inputted successfully up to the stop bit the RDRF bit is set to 1 If an overrun parity or framing error occurs the corresponding error flag bit PER OVE or FER is set to 1 These bits are set when a stop bit is detected If reception interrupt enable bit has been enabled SMC2 RIE 1 an interrupt request to the interrupt controller will be generated CHAPTER 8 INTERRUPTS ...

Page 357: ...s set up in the following procedure Initial setup 1 Set the port input DDR1 2 Set the interrupt level ILR1 3 Set the prescaler PSSR 4 Set the baud rate BRSR 5 Select the clock SMC10 CKS 6 Set the operation mode SMC10 MD 7 Enable disable the serial clock output SMC20 SCKE 8 Enable reception SMC20 RXE 1 9 Enable interrupts SMC20 RIE 1 Interrupt processing 1 Read receive data RDR0 Table 20 7 1 Operat...

Page 358: ... about the dedicated baud rate generator refer to CHAPTER 21 UART SIO DEDICATED BAUD RATE GENERATOR Figure 20 7 1 Baud Rate Calculation when Using Dedicated Baud Rate Generator Baud rate value Machine clock MCLK bps 4 1 2 4 8 2 255 UART baud rate setting register BRSR Baud rate setting BRS7 to BRS0 UART prescaler selection register PSSR Prescaler selection PSS1 PSS2 Table 20 7 2 Sample Asynchronou...

Page 359: ... H level by performing the specified data bit length transfer with MSB or LSB first LSB first or MSB first can be selected by the BDS bit It becomes H level at the idle state Figure 20 7 2 Transfer Data Format Table 20 7 3 Baud Rate Setting Range in Clock Asynchronous Mode PSS 1 0 BRS 7 0 0 0 to 1 1 02H 2 to FFH 255 ST D0 D1 D2 D3 D4 SP ST D0 D1 D2 D3 D4 P SP ST D0 D1 D2 D3 D4 SP SP ST D0 D1 D2 D3...

Page 360: ...ter RDR0 stores data the receive data register full RDRF bit is set to 1 A reception interrupt occurs the moment the receive data register full RDRF bit is set to 1 when the reception interrupt enable bit RIE contains 1 Received data is read from the UART SIO serial input data register RDR0 after each error flag PER OVE FER in the UART SIO serial status and data register is checked When received d...

Page 361: ...ol bit PEN contains 1 2 Framing error FER The framing error FER bit is set to 1 if 1 is not detected at the position of the first stop bit in serial data received in the set character bit length CBL under parity control PEN Note that the stop bit is not checked if it appears at the second bit or later 3 Overrun error OVE Upon completion of reception of serial data the overrun error OVE bit is set ...

Page 362: ...ered circuit is activated upon detection of the start bit and serial data is inputted to the reception shift register at intervals of four periods of BRCLK When data is received sampling is performed at three points of the baud rate clock BRCLK and data sampling clock DSCLK and received data is confirmed on a majority basis when two bits out of three match Figure 20 7 5 Start Bit Detection and Ser...

Page 363: ...ansmit data register empty TDRE is set to 1 When the transmission interrupt enable bit TIE contains 1 a transmission interrupt occurs if the transmit data register empty TDRE bit is set to 1 This allows the next piece of transmit data to be written to the UART SIO serial output data register TDR0 by interrupt handling To detect the completion of serial transmission by transmission interrupt set th...

Page 364: ...to 1 Concurrent transmission and reception In asynchronous clock mode UART transmission and reception can be performed independently Therefore transmission and reception can be performed at the same time or even with transmitting and receiving frames overlapping each other in shifted phases UO D0 D1 TDRE Transmission interrupt TXE 1 Writing of transmit data D2 D3 Data transfer from UART SIO serial...

Page 365: ... to 0 To output the dedicated baud rate generator output as a shift clock signal set the SCKE bit to 1 The serial clock signal is obtained by dividing clock by two which is supplied by the dedicated baud rate generator The baud rate in the SIO mode can be set in the following range For more information about the dedicated baud rate generator also refer to CHAPTER 21 UART SIO DEDICATED BAUD RATE GE...

Page 366: ...re set transmission control TXE 1 to write dummy transmit data to the UART SIO serial output register Refer to the data sheet for the UCK clock value Reception in UART SIO operation mode 1 For reception in operation mode 1 each register is used as follows Baud rate value Machine clock MCLK bps 2 1 2 4 8 1 256 UART baud rate setting register BRSR Baud rate setting BRS7 to BRS0 UART prescaler select...

Page 367: ... 1 then write transmit data to the UART SIO serial output data register to generate the serial clock signal and start reception SCM10 UART SIO serial mode control register 1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Bit No BDS PEN TDP SBL CBL1 CBL0 CKS MD SMC10 1 SCM20 UART SIO serial mode control register 2 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Bit No SCKE TXOE RERC RXE TXE RIE TCIE TEIE SMC20 0 ...

Page 368: ... read received data read it from the UART SIO serial input data register after checking the error flag OVE in the UART SIO serial status and data register When received data is read from the UART SIO serial input data register RDR0 the receive data register full RDRF bit is cleared to 0 Figure 20 7 12 8 bit Reception of Synchronous CLK Mode Operation when reception error occurs When an overrun err...

Page 369: ...tput data register TDR0 the transmit data register empty TDRE bit is cleared to 0 When serial transmission is started after transmit data is transferred from the UART SIO serial output data register TDR0 to the transmission shift register the transmit data register empty TDRE bit is set to 1 SCM10 UART SIO serial mode control register 1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Bit No BDS PEN TDP SB...

Page 370: ... is set to 1 and a transmission completion interrupt occurs Figure 20 7 14 8 bit Transmission in Synchronous CLK Mode Concurrent transmission and reception When external clock is enabled Transmission and reception can be performed independently of each other Transmission and reception can therefore be performed at the same time or even when their phases are shifted from each other and overlapping ...

Page 371: ...etting is used How to enable stop UART operation The reception operation enable bit SMC20 RXE is used Operation mode Operation mode selection MOD Mode 0 Asynchronous clock mode UART Set the bit to 0 Mode 1 Synchronous clock mode SIO Set the bit to 1 Clock input Clock selection CKS When selecting dedicated baud rate generator Set the bit to 0 When selecting external clock Set the bit to 1 UART When...

Page 372: ... bit to 0 Enabling transmission Set the bit to 1 Operation Parity control SMC10 PEN Parity polarity SMC10 TDP When selecting no parity Set the bit to 0 When selecting even parity Set the bit to 1 Set the bit to 0 When selecting odd parity Set the bit to 1 Set the bit to 1 Operation Data length selection bit CBL 1 0 When selecting 5 bit length Specify 00 When selecting 6 bit length Specify 01 When ...

Page 373: ...t the baud rate Refer to 20 7 1 Operating Description of Operation Mode 0 Interrupt related registers The interrupt level setting registers shown in the following table are used to set the interrupt level What is controlled Serial data direction control BDS When selecting LSB transfer from least significant bit Set the bit to 0 When selecting MSB transfer from most significant bit Set the bit to 1...

Page 374: ...IE Transmission completion interrupt enable bit TCIE Transmission data register empty interrupt enable bit TEIE When disabling interrupt requests Select 0 When enabling interrupt requests Select 1 UART reception UART transmission When clearing interrupt requests Read from UART SIO serial input register RDR0 to clear reception data register full bit RDRF Write data to UART SIO serial output data re...

Page 375: ...operations of the dedicated baud rate generator of UART SIO 21 1 Overview of UART SIO Dedicated Baud Rate Generator 21 2 Channels of UART SIO Dedicated Baud Rate Generator 21 3 Registers of UART SIO Dedicated Baud Rate Generator 21 4 Operating Description of UART SIO Dedicated Baud Rate Generator ...

Page 376: ... rate generator baud rate setting register BRSR Block Diagram of UART SIO Dedicated Baud Rate Generator Figure 21 1 1 Block Diagram of UART SIO Dedicated Baud Rate Generator Input Clock The UART SIO dedicated baud rate generator uses the output clock from the prescaler or the machine clock as its input clock Output Clock The UART SIO dedicated baud rate generator supplies its clock to the UART SIO...

Page 377: ...tor This series contains 1 channel of the UART SIO dedicated baud rate generator The following table shows the correspondence the channel and registers ch Channel Table 21 2 1 Registers of Dedicated Baud Rate Generator Channel Register name Corresponding register Name in this manual 0 PSSR0 UART SIO dedicated baud rate generator prescaler selection register ch 0 BRSR0 UART SIO dedicated baud rate ...

Page 378: ...rs Related to UART SIO Dedicated Baud Rate Generator UART SIO dedicated baud rate generator prescaler selection register PSSR Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 0FBEH PSSR0 BRGE PSS1 PSS0 00000000B R0 WX R0 WX R0 WX R0 WX R0 WX R W R W R W UART SIO dedicated baud rate generator baud rate setting register BRSR Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value ...

Page 379: ...rns 0 bit2 BRGE Baud rate clock output enable This bit enables the output of the baud rate clock BRCLK Setting the bit to 1 loads BRS 7 0 to the 8 bit down counter and outputs BRCLK which is supplied to the UART SIO Setting the bit to 0 stops the output of BRCLK bit1 0 PSS1 0 Prescaler selection R W Readable writable Read value is the same as write value R0 WX Undefined bit Read value is 0 writtin...

Page 380: ...ing Register BRSR Figure 21 3 3 UART SIO Dedicated Baud Rate Generator Baud Rate Setting Register BRSR This register sets the cycle of the 8 bit down counter and can be used to set any baud rate clock Write to the register when the UART is stopped Do not set BRSR 7 0 to 00H or 01H in clock asynchronous mode Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 0FBFH BRSR0 BRS7 BRS6 BRS5 BR...

Page 381: ...in UART mode within the following range Table 21 4 1Sample Asynchronous Transfer Rates by Baud Rate Generator Machine Clock 10MHz UART SIO Dedicated baud rate generator setting UARTinternal division Total division ratio PSS x BRS x4 Baud rate 10MHz Total division ratio Prescaler selection PSS 1 0 Baud rate counter setting BRS 7 0 1 Setting value 0 0 20 4 80 125000 1 Setting value 0 0 22 4 88 11363...

Page 382: ...368 CHAPTER 21 UART SIO DEDICATED BAUD RATE GENERATOR ...

Page 383: ...perations of the I2 C 22 1 Overview of I2 C 22 2 I2 C Configuration 22 3 I2 C Channels 22 4 I2 C Bus Interface Pins 22 5 I2C Registers 22 6 I2C Interrupts 22 7 I2C Operations and Setup Procedure Examples 22 8 Notes on Use of I2 C 22 9 Sample Programs for I2 C ...

Page 384: ... a master slave relationship between devices Also the I2C interface can connect multiple devices provided the bus capacitance does not exceed an upper limit of 400 pF The I2 C interface is a true multi master bus with collision detection and a communication control protocol that prevent loss of data even if more than one master attempts to start a data transfer at the same time The communication c...

Page 385: ...ock selector Clock divider Shift clock generator Start stop condition generation circuit Start stop condition detection circuit Arbitration lost detection circuit Slave address comparison circuit IBSR register IBCR registers IBCR00 IBCR10 ICCR0 register IAAR0 register IDDR0 register ...

Page 386: ...enable Bus busy Repeat start Last bit Transmit receive Arbitration lost detection circuit SDA line SCL I line First byte I C enable Start stop condition detection circuit ICCR0 EN CS2 CS1 CS0 RSC LRB TRX FBT BB IBCR10 Transfer interrupt End 8 5 Machine clock Shift clock edge DMBP CS4 CS3 6 7 8 22 4 2 AAS GCA Slave IDDR0 register IAAR0 register Slave address comparison circuit IBSR0 General call St...

Page 387: ...set to 1 and the master changes to a slave automatically Slave address comparison circuit The slave address comparison circuit receives the slave address after the start condition to compare it with its own slave address The address is seven bit data followed by a data direction R W bit in the eighth bit position If the received address matches the own slave address the comparison circuit transmit...

Page 388: ...ins and registers respectively ch Channel Table 22 3 1 I2 C Pins Channel Pin name Pin function 0 SCL0 SDA0 I2C bus I O Table 22 3 2 I2 C Registers Channel Register name Register designation Representation in this manual 0 IBCR00 I2 C bus control register 0 IBCR10 I2C bus control register 1 IBSR0 I2 C bus status register IDDR0 I2 C data register IAAR0 I2C address register ICCR0 I2C clock control re...

Page 389: ...SDA0 pin is automatically set as a data I O pin to function as the SDA0 terminal To use it as an input pin enable the I2C operation ICCR0 EN 1 and write 0 to the corresponding of bit 4 port direction register DDR SCL0 pin The SCL0 pin can serve as a N ch open drain I O port external interrupt input hysteresis input serial data input hysteresis input for eight bit serial I O or I2 C serial clock I ...

Page 390: ...376 CHAPTER 22 I2C ...

Page 391: ...WX R WX R WX R WX R WX R WX R WX R WX I2C data register IDDR0 Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 0063H IDDR0 D7 D6 D5 D4 D3 D2 D1 D0 00000000B R W R W R W R W R W R W R W R W I2 C address register IAAR0 Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 0064H IAAR0 A6 A5 A4 A3 A2 A1 A0 00000000B R0 WX R W R W R W R W R W R W R W I2C clock control register ICCR...

Page 392: ...ad modfy write instruction Initial value WUE MCU standby mode wakeup function enable bit 0 Disables the MCU standby mode wakeup function in stop watch mode 1 Enables the MCU standby mode wakeup function in stop watch mode WUF MCU standby mode wakeup interrupt request flag bit Read Write 0 Start condition undetected Clear 1 Start condition detected Unchanged SPF Stop detection interrupt request fla...

Page 393: ...s bit for example using a previous transfer completion interrupt to read latest received data The latest data ACK IBSR0 LRB can be read after the ACK has been received IBSR0 LRB must be read during the transfer completion interrupt in the ninth SCL cycle If ACK is read when this bit is 1 therefore you must write 0 to this bit in the transfer completion interrupt in the eighth SCL0 cycle so that an...

Page 394: ...pt request is generated to start I2 C operation Note Write 1 to this bit immediately before the MCU enters the stop or watch mode To ensure that I2 C operation can restart immediately after the MCU wakes up from stop or watch mode clear write 0 to this bit as soon as possible When a wakeup interrupt request occurs the MCU wakes up after the oscillation stabilization wait time elapses To prevent th...

Page 395: ...381 CHAPTER 22 I2C ...

Page 396: ...etected Unchanged DACKE Data acknowledge enable bit 0 Disables data ACK 1 Enables data ACK MSS Master slave select bit 0 Selects slave mode 1 Selects master mode SCC Start condition generation bit Read Write 0 Always 0 Unchanged 1 Generates master mode repeated start condition INTE Transfer completion interrupt enable bit 0 Disables data transfer completion interrupt requests 1 Enables data transf...

Page 397: ...enerates a start condition and then starts address transfer Writing 0 to the bit while the I2C bus is in the busy state IBSR0 BB 1 selects slave mode generates a stop condition and then ends data transfer If arbitration lost occurs during data or address transfer in master mode this bit is cleared to 0 and the mode changes to slave mode Note Do not set IBCR10 SCC 1 and IBCR10 MSS 0 at the same tim...

Page 398: ...o 0 in the following cases 0 written to the bit Repeated start condition IBCR10 SCC 1 or stop condition IBCR10 MSS 0 occurred in master mode An attempt to write 1 to this bit leaves its value unchanged and has no effect on the operation The bit returns 1 when read by a read modify write operation The SCL0 line remains at L while this bit is 1 Writing 0 to clear the bit change the value to 0 releas...

Page 399: ...385 CHAPTER 22 I2C ...

Page 400: ...tart condition detected with bus in use BB Bus busy bit 0 Bus idle 1 Bus busy TRX Data transfer status bit 0 Receive mode 1 Transmit mode LRB Acknowledge storage bit 0 Acknowledgment detected in ninth shift clock cycle 1 Acknowledgment not detected in ninth shift clock cycle GCA General call address detection bit 0 General call address 00H not received in slave mode 1 General call address 00H rece...

Page 401: ...triggered by the eighth SCL0 cycle so that another transfer completion interrupt will be triggered by the ninth SCL0 cycle bit3 TRX Data transfer status bit This bit indicates the data transfer mode This bit is set to 1 when data transfer is performed in transfer mode This bit is set to 0 in the following cases Data is transferred in receive mode NACK is received in slave transmit mode bit2 AAS Ad...

Page 402: ... or when a repeated start condition is generated writing 1 to the IBCR10 SCC bit Each bit of the shift register data is output shifted to the SDA0 line Note that writing to this register has no effect on the current data transfer In slave mode however data is transferred to the shift register after the address is determined The received data or address can be read from this register during the tra...

Page 403: ...slave address In slave mode address data from the master is recieved and then compared with the value of the IAAR register I2 C address register IAAR0 Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 0064H IAAR0 A6 A5 A4 A3 A2 A1 A0 00000000B R0 WX R W R W R W R W R W R W R W R W Readable writable Read value is the same as write value R0 WX Undefined bit Read value is 0 writing has no...

Page 404: ...R0 WX R W R W R W R W R W R W CS4 CS3 Clock 1 select bits Divider m 0 0 5 0 1 6 1 0 7 1 1 8 EN I2 C operation enable bit 0 Disables I2 C operation 1 Enables I2 C operation DMBP Divider m bypass bit 0 Disables bypassing 1 Bypasses divider m CS2 CS1 CS0 Clock 2 select bits Divider n 0 0 0 4 0 0 1 8 0 1 0 22 0 1 1 38 1 0 0 98 1 0 1 128 1 1 0 256 1 1 1 512 R W Readable writable Read value is the same ...

Page 405: ... write to the bit is meaningless bit5 EN I2 C operation enable bit This bit enables I2 C interface operation Setting the bit to 1 Enables operation of the I2 C interface This bit is set to 0 in the following cases When 0 is written to this bit When IBCR10 BER is 1 Setting the bit to 0 Disables operation of the I2 C interface and clears the following bits to 0 AACKX INTS and WUE bits in the IBCR00 ...

Page 406: ... to 1 regardless of the value of the IBCR10 INTE bit Interrupt in response to a bus error When the following conditions are met a bus error is deemed to have occurred and the I2 C interface will be stopped When a stop condition is detected in master mode When a start or stop condition is detected during transmission or reception of the first byte When a start or stop condition is detected during t...

Page 407: ...o enable IBCR00 ALE 1 Either write 0 to the arbitration lost interrupt request flag bit IBCR00 ALF while the bus is idle or write 0 to the IBCR10 INT bit from the interrupt service routine while the bus is busy to clear the interrupt request When arbitration lost occurs the IBCR00 ALF bit is set to 1 regardless of the value for the IBCR00 ALE bit Interrupt for MCU wakeup from stop watch mode When ...

Page 408: ...e same interrupt request number and vector table as the 16 bit reload timer ch 1 Table 22 6 3 Registers and Vector Table Related to I2C Interrupts Interrupt source Interrupt request No Interrupt Level Setting register Vector table address Register Setting bit Upper Lower ch 0 IRQ16 ILR4 L16 FFDAH FFDBH ...

Page 409: ...ion The wakeup function wakes up the MCU upon detection of a start condition from low power consumption mode such as stop or watch mode Setup Procedure Examples Use the following procedure to set up I2 C Initialization 1 Set the port for input DDR0 2 Set the interrupt level ILR2 ILR4 3 Set the slave address IAAR0 4 Select the clock and enable I2C operation ICCR0 5 Enable bus error interrupt reques...

Page 410: ...n and arbitration function to prevent data from being lost if more than one master attempts to start data transfer at the same time I2C Protocol Figure 22 7 1 shows the format required for data transfer Figure 22 7 1 Data Transfer Example The slave address is transmitted after a start condition S is generated This address is seven bits followed by the data direction bit R W in the eighth bit posit...

Page 411: ...ave address and the data transfer direction R W bit bit 0 of IDDR0 The acknowledgment from the slave is received after the address data is sent SDA0 goes to L in the ninth clock cycle and the acknowledge bit from the receiving device is received see Figure 22 7 1 In this case the R W bit IDDR0 bit0 is inverted logically and stored in the IBSR0 TRX bit as 1 if the SDA level is L Addressing in slave...

Page 412: ...erated if an address acknowledgment has already been generated and IBCR10 DACKE 1 The received acknowledgment is saved in IBSR0 LRB in the ninth SCL0 cycle If the data ACK depends on the content of received data such as packet error checking used by the SM bus control the data ACK by setting the data ACK enable bit IBCR10 DACKE after writing 1 to the IBCR00 INTS bit for example by a previous trans...

Page 413: ...10 GACKE 1 ACK is given and IBSR0 GCA is set IBCR10 INT is set at 9th SCL Set IBCR00 INTS 1 IBCR10 INT is set at 9th SCL Read IBSR0 LRB IBCR10 INT is set at 8th SCL Read IDDR0 and control ACK NACK by IBCR10 DACKE To read IBSR10 LRB set INTS 0 IBCR10 INT is set at 8th SCL Read IDDR0 and control ACK NACK by IBCR10 DACKE To read IBSR10 LRB set INTS 0 ACK is given and IBSR0 GCA is set ACK is given and...

Page 414: ...e data output is halted and IBCR00 ALF is set to 1 If this occurs an interrupt is generated if arbitration lost interrupts have been enabled IBCR00 ALE 1 If IBCR00 ALF is set to 1 the module sets IBCR10 MSS 0 and IBSR0 TRX 0 clears TRX and goes to slave receive mode If IBCR00 ALF is set to 1 when IBSR0 BB 0 IBCR00 ALF is cleared only by writing 0 If IBCR00 ALF is set to 1 when IBSR0 BB 1 IBCR00 AL...

Page 415: ...use the following procedure to set up the module from the software 1 Trigger a start condition from the program by setting the IBCR10 MSS bit to 1 2 Check the IBCR00 ALF and IBSR0 BB bits in the arbitration lost interrupt If IBCR00 ALF 1 and IBSR0 BB 0 clear the IBCR00 ALF bit to 0 If IBCR00 ALF 1 and IBSR0 BB 1 clear the IBCR00 ALE bit to 0 and perform control as normal Normal control means writi...

Page 416: ...ALF bit 1 Figure 22 7 6 Timing Diagram with Interrupt Generated with IBCR00 ALF Bit 1 Detected Set master mode Set the MSS bit in I2 C bus control register 1 IBCR10 to 1 no Enable AL interrupts IBCR00 ALE 1 IBCR00 ALF 1 IBSR0 BB 0 yes yes no Normal control Write 0 to IBCR00 ALF to clear AL flag and interrupt Write 0 to IBCR00 ALE to clear AL interrupt Data Slave address Start condition Interrupt i...

Page 417: ...top and watch modes Note In PLL stop mode a PLL oscillation stabilization wait time is required in addition to the oscillation stabilization wait time This causes a very long delay between the MCU waking up and communications restarting Figure 22 7 7 Comparison of Normal I2C Operation and Wakeup Operation SDA0 SCL0 IRQ by IBCR00 WUF Machine Clock 1 2 3 4 5 1 Set the IBCR00 WUE bit to 1 immediately...

Page 418: ...rates the wakeup function Figure 22 7 8 Sample Flow NO Go to stop watch mode YES IBCR00 WUE 0 Enable wakeup function by setting IBSR0 BB 0 IBSR0 BB 0 YES NO Procedure for transition to stop watch mode Write 0 to IBCR00 ALE and clear AL interrupt IBCR00 WUE 1 ...

Page 419: ...n between next byte transfer and start condition When 1 is written to IBCR10 SCC with IBCR10 INT cleared the SCC bit takes priority and a start condition develops Notes on setup using software Do not select a repeated start condition IBCR10 SCC 1 and slave mode IBCR10 MSS 0 simultaneously Execution cannot return from interrupt processing if the interrupt request enable bit is enabled IBCR10 BEIE 1...

Page 420: ...estart as soon as possible When a wakeup interrupt request occurs the MCU wakes up after the oscillation stabilization wait time elapses To prevent the data loss immediately after wakeup design the system so that the SCL0 rises as the first cycle and the first bit must be transmitted as data after 100 μs assuming a minimum oscillation stabilization wait time of 100 μs from the wakeup due to start ...

Page 421: ...r slave mode Use the master slave select bit IBCR10 MSS Selecting the shift clock Use the clock select bits ICCR0 CS4 CS3 CS2 CS1 CS0 Bypassing the m divider when the shift clock frequency is generated Use the divider m bypass bit ICCR0 DMBP Control I2 C operation enable bit EN To disable I2 C operation Set the bit to 0 To enable I2C operation Set the bit to 1 Control Master slave select bit MSS T...

Page 422: ...wledge disable bit AACKX To enable address acknowledge output Set the bit to 0 To disable address acknowledge output Set the bit to 1 Control Data acknowledge enable bit DACKE To enable data acknowledge output Set the bit to 1 To disable data acknowledge output Set the bit to 0 Control General call address acknowledge enable bit GACKE To enable general call address acknowledge output Set the bit t...

Page 423: ...nterrupt request enable bit IBCR10 BEIE To clear interrupt requests use the interrupt request flag IBCR10 BER Interrupt source Interrupt level setting register Interrupt vector ch 0 Interrupt level register ILR2 Address 0007BH 10 Address 0FFE6H Control Interrupt request enable bit INTE To disable interrupt requests Set the bit to 0 To enable interrupt requests Set the bit to 1 Control Interrupt re...

Page 424: ...upt requests use the interrupt request flag IBCR00 WUF Control Interrupt request enable bit SPE To disable interrupt requests Set the bit to 0 To enable interrupt requests Set the bit to 1 Control Interrupt request flag SPF To clear interrupt requests Write 0 to the flag Control Interrupt request enable bit ALE To disable interrupt requests Set the bit to 0 To enable interrupt requests Set the bit...

Page 425: ...0 bit A D Converter 23 2 Configuration of 10 bit A D Converter 23 3 Pins of 10 bit A D Converter 23 4 Registers of 10 bit A D Converter 23 5 Interrupts of 10 bit A D Converter 23 6 Operations of 10 bit A D Converter and Its Setup Procedure Examples 23 7 Notes on Use of 10 bit A D Converter 23 8 Sample Programs for 10 bit A D Converter ...

Page 426: ... an analog input pin to 10 bit digital values One of multiple analog input pins can be selected The conversion speed is programmable to be configured selected according to the operating voltage and frequency An interrupt is generated when A D conversion completes The completion of conversion can also be checked with the ADI bit in the ADC1 register To activate A D conversion functions follow one o...

Page 427: ...ADDL A D control register 1 ADC1 A D control register 2 ADC2 Block Diagram of 10 bit A D Converter Figure 23 2 1 Block Diagram of 10 bit A D Converter AD8 TIM1 TIM0 ADCK ADIE EXT CKDIV1CKDIV0 ANS3 ANS2 ANS1 ANS0 ADI ADMV ADMVX AD A D control register 2 ADC2 Analog channel selector A D control register 1 ADC1 Sample and hold circuit Control circuit A D data registers ADDH ADDL Vcc IRQ Internal data...

Page 428: ... based on the voltage compare signals from the comparator When conversion is completed the A D conversion function sets the interrupt request flag bit ADC1 ADI A D data registers ADDH ADDL The high order two bits of 10 bit A D data are stored in the ADDH register the low order eight bits are stored in the ADDL register Setting the A D conversion precision bit ADC2 AD8 to 1 provides 8 bit precision...

Page 429: ...n by selecting it using the analog input channel select bits ADC1 ANS0 to ANS3 with the corresponding bit in the port direction register DDR set to 0 Even when the 10 bit A D converter is used the pins not used for analog input can be used as general purpose I O ports Note that the number of analog input pins differs depending on the series ADTG Pin ADTG This is a pin used to activate A D conversi...

Page 430: ...416 CHAPTER 23 10 BIT A D CONVERTER ...

Page 431: ...1 W Readable writable Read value is different from write value 1 is read by read modify write instruction A D control register 1 ADC1 Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 006CH ANS3 ANS2 ANS1 ANS0 ADI ADMV ADMVX AD 00000000B R W R W R W R W R RM1 W R WX R W R0 W A D control register 2 ADC2 Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 006DH AD8 TIM1 TIM0 AD...

Page 432: ...0 pin ANS3 0 AN01 pin 0 AN03 pin Interrupt request flag bit Read Write Conversion not completed ADI Clear this bit 0 Conversion completed 1 Make no changes to the bit with no effect on others AN02 pin 0 0 0 0 0 ANS2 ANS3 ANS2 ANS1 ANS0 ADI ADMV ADMVX AD Current cut off analog switch control bit Turn on analog switch only during conversion Maintain analog switch on ADMVX 0 1 Conversion flag bit Not...

Page 433: ...t returns 1 bit2 ADMV Conversion flag bit Indicates that conversion is ongoing during execution of the A D conversion function The bit contains 1 during conversion This bit is read only Any value attempted to be written is meaningless and has no effect on operation bit1 ADMVX Analog switch control bit Controls the analog switch for shutting down the internal reference power supply When the externa...

Page 434: ...t output ADIE 0 1 Clock CKIN select bits 1 MCLK CKDIV1 0 2 MCLK 0 8 MCLK 4 MCLK 1 0 1 1 1 CKDIV0 Precision select bit 10 bit precision 8 bit precision AD8 0 1 AD8 TIM1 TIM0 ADCK ADIE EXT CKDIV1 CKDIV0 Continuous conversion enable bit Start using the AD bit in the ADC1 register Continuous activation with the clock selected by the ADCK bit in the ADC2 register EXT 0 1 External start signal select bi...

Page 435: ...IV1 DKDIV0 Note Update this bit only with A D operation stopped bit4 ADCK External start signal select bit Selects the start signal for external start ADC2 EXT 1 bit3 ADIE Interrupt request enable bit Enables or disables output of interrupts to the interrupt controller Interrupt requests are output with both of this bit and the interrupt request flag bit ADC1 ADI set to 1 bit2 EXT Continuous activ...

Page 436: ...n functions When A D conversion is started the results of conversion are finalized and stored in these registers after the conversion time according to the register settings has passed After A D conversion finishes therefore read the A D data registers conversion results write 0 to the ADI bit bit 3 in the ADC1 register before the next A D conversion terminates then after A D conversion finishes c...

Page 437: ...equest The ADI bit is set when A D conversion is completed irrespective of the value of the ADIE bit The CPU cannot return from interrupt processing if the interrupt request flag bit ADC1 ADI is 1 with interrupt requests enabled ADC2 ADIE 1 Be sure to clear the ADI bit within the interrupt service routine Register and Vector Table Related to 10 bit A D Converter Interrupts The interrupt request nu...

Page 438: ...3 6 1 are required for software activation of the A D conversion function Figure 23 6 1 Settings for A D Conversion Function Software Activation When A D conversion is activated the A D conversion function starts working In addition even during conversion the A D conversion function can be reactivated bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ADC1 ANS3 ANS2 ANS1 ANS0 ADI ADMV ADMVX AD 1 ADC2 AD8 TIM...

Page 439: ...uit compares the voltage loaded into the sample and hold capacitor with the A D conversion reference voltage from the most significant bit MSB to the least significant bit LSB and then sends the results to the ADDH and ADDL registers After the results have been completely transferred the conversion flag bit is cleared ADC1 ADMV 0 and the interrupt request flag bit is set ADC1 ADI 1 Notes When the ...

Page 440: ...e A D input ADC1 ANS0 to ANS3 4 Set the sampling time ADC2 TIM1 TIM0 5 Select the clock ADC2 CKDIV1 CKDIV0 6 Set A D conversion properties ADC2 AD8 7 Select the operation mode ADC2 EXT 8 Select the startup trigger ADC2 ADCK 9 Enable interrupts ADC2 ADIE 1 10 Activate A D ADC1 AD 1 Interrupt processing 1 Clear the interrupt request flag ADC1 ADI 0 2 Read converted values ADDH ADDL 3 Activate A D AD...

Page 441: ... If A D conversion is reactivated ADC1 AD 1 and terminated at the same time the interrupt request flag bit ADC1 ADI is set Error As VCC VSS decreases an error increases relatively 10 bit A D converter and analog input power on shut down sequences Turn on the 10 bit A D converter power supply VCC and analog input AN00 to AN07 at the same as or after turning on the digital power supply DVCC In addit...

Page 442: ... internal reference power shutdown of the 10 bit A D converter Use the analog switch control bit ADC1 ADMVX to control the internal reference power shutdown analog switch Selecting the 10 bit A D converter activation method Use the continuous activation enable bit ADC2 EXT to select the startup trigger Generating a software trigger Use the A D conversion start bit ADC1 AD to generate a software tr...

Page 443: ...clock External start signal select bit ADC2 ADCK To select the ADTG input pin Set the bit to 0 To select the 8 16 bit composite timer TDO0 Set the bit to 1 Operating mode Precision select bit AD8 To select 10 bit precision Set the bit to 0 To select 8 bit precision Set the bit to 1 Operation Analog input channel select bits ANS 3 0 To use the AN0 pin Set the pins to 0000 To use the AN1 pin Set the...

Page 444: ...t request enable bit ADC2 ADIE To clear interrupt requests use the interrupt request bit ADC1 ADI ADI Meaning The value read is 0 A D conversion completed with no interrupt request The value read is 1 A D conversion completed with interrupt request generated ADMV Setting The value read is 0 A D conversion completed suspended The value read is 1 A D conversion in progress Interrupt level setting re...

Page 445: ...and operations of the LCD controller 24 1 Overview of LCD Controller 24 2 Configuration of LCD Controller 24 3 Pins of LCD Controller 24 4 Registers of LCD Controller 24 5 LCD Controller Display RAM 24 6 Operations of LCD Controller 24 7 Notes on Use of LCD Controller ...

Page 446: ...e The number of segment outputs depends on each series 14 bytes 28 x 4 bits of display RAM integrated The display RAM size depends on each series Main clock or subclock selectable only in product with dual clock system as the operating clock Blinking function limited to some pins product with dual clock system Capable of directly driving the LCD panel Duty selectable from among 1 2 1 3 and 1 4 res...

Page 447: ...Common driver Segment driver Divider resistor LCD Controller Block Diagram Figure 24 2 1 LCD Controller Block Diagram LCDC control register LCDCC This register is used to select the clock for generating the frame period select display or display blanking select the display mode select the frame period clock and control the LCD driving LCDC control register LCDCC LCDC enable registers 1 to 5 LCDCE1...

Page 448: ... selection from amongst the eight frequencies generated from the two clocks Timing control The common and segment signals are controlled based on the frame frequency and register settings AC waveform generator circuit This block generates AC waveforms for driving the LCD from timing control signals Common driver This block is the driver of the LCD common pins Segment driver This block is the drive...

Page 449: ...tors without connecting the external divider resistors set the VSEL bit to 1 Even when using internal split resistors set the VE1 bits in LCDC enable register 1 LCDCE1 to 1 When internal split resistors are used the V3 to V1 pins cannot be used as general purpose output ports The LCD controller stops upon transition to main stop or watch mode STBC TMD 1 while operation in main stop and watch modes...

Page 450: ...r resistors for brightness control Figure 24 2 3 States with Internal Divider Resistors Used Figure 24 2 4 Brightness Control with Internal Divider Resistors Used As the internal 2R resistor is enabled during LCD operation connect the VR resistor in parallel with the 2R resistor 2R R R R LCDC enabled N ch V3 V2 V1 Vcc V3 V2 V1 2R R R R LCDC enabled N ch V3 V2 V1 Vcc V2 V1 1 2 bias 1 3 bias V3 5V p...

Page 451: ...connect external divider resistors to the LCD drive power supply pins V1 to V3 instead Figure 24 2 5 shows an example of connecting external divider resistors and Table 24 2 1 lists the LCD drive voltage settings for the bias method Figure 24 2 5 Example of Connecting External Divider Resistors V1 to V3 Voltages at V1 to V3 pins VLCD LCD operating voltage Vcc V3 V2 V1 1 2 bias R R VLCD Vcc V3 V2 V...

Page 452: ...CC VSEL to disconnect all the internal divider resistors Write 1 to the V3 to V1 select bits in LCDC enable register 1 LCDCE1 VE1 so that the target ports can be used as power supply pins to drive the LCD 2 When the internal divider resistors are disconnected writing a value other than 00B to the display mode select bits MS1 and MS0 in the LCDC control register turns on the LCDC enable transistor ...

Page 453: ...g bits in the LCDC enable registers LCDCE1 to 5 to 1 To use LCD pins for ports set the PICTL bit in LCDC enable register 1 LCDCE1 to 1 and the corresponding select bits COM SEG in LCDC enable registers 1 to 5 to 0 COM0 to COM3 pins The COM0 to COM3 pins are LCD common outputs These pins also serve as I O ports SEG0 to SEG23 SEG28 to SEG31 pins The SEG0 to SEG23 SEG28 to SEG31 pins are LCD segment ...

Page 454: ...o V3 PDR read PDR write PDR DDR read DDR write DDR PUL read PUL write PUL 0 1 1 0 Peripheral function output Peripheral function output enable Peripheral function input Pin Stop Watch SPL 1 Internal bus In bit operation instruction Pull up Selectalbe only P94 and P95 ILSR2 read ILSR2 write ILSR2 Hysteresis Automotive ...

Page 455: ...24 3 2 Block Diagram of LCD related Pins COM0 to COM3 PDR read PDR write PDR DDR read DDR write DDR 0 1 LCD enable LCD output Pin Stop watch SPL 1 At bit operation instruction Internal bus ILSR2 read ILSR2 ILSR2 write Hysteresis Automotive ...

Page 456: ...struction Internal bus ILSR3 read ILSR3 ILSR3 write Hysteresis Automotive Peripheral function input Peripheral function input enable Peripheral function output enable Peripheral function output 0 1 Selectable only PB0 PDR read PDR write PDR DDR read DDR write DDR 0 1 Pin Stop Watch SPL 1 Internal bus Peripheral function input enable Peripheral function input In bit operation instruction ILSR3 read...

Page 457: ...on input enable Peripheral function input Pin Stop Watch SPL 1 Internal bus In bit operation instruction ILSR2 read ILSR2 write ILSR2 Hysteresis Automotive LCD output enable LCD output PDR read PDR write PDR DDR read DDR write DDR AIDRL read AIDRL write AIDRL 0 1 Peripheral function input enable Peripheral function input Pin Stop watch SPL 1 At bit operation instruction A D analog input ILSR2 read...

Page 458: ...elated Pins S28 to S31 PDR read PDR write PDR DDR read DDR write DDR 0 1 LCD enable LCD output Pin Stop watch SPL 1 At bit operation instruction Internal bus ILSR3 read ILSR3 write ILSR3 Peripheral function input enable Peripheral function input Automotive Hysteresis ...

Page 459: ...CE3 Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 0FC7H SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG09 SEG08 00000000B R W R W R W R W R W R W R W R W LCDC enable register 4 LCDCE4 Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 0FC8H SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 00000000B R W R W R W R W R W R W R W R W LCDC enable register 5 LCDCE5 Address bit7 bit6 bi...

Page 460: ... FCL 210 x N FCL 0 MS1 0 0 1 0 1 1 1 MS0 Display mode select bits LCD operation halt 1 2 duty output mode time division number N 2 1 3 duty output mode time division number N 3 1 4 duty output mode time division number N 4 Display blanking select bit Display Display blanking BK 0 1 LCD drive power supply control bit With internal divider resistors selected Use external divider resistors VSEL 0 Use...

Page 461: ...ue operating in main stop or watch mode bit5 VSEL LCD driving power control bit In models with internal divider resistors this bit selects whether to energize the internal divider resistors Setting the bit to 0 Shuts off the internal divider resistors Setting the bit to 1 Energizes the internal divider resistors To connect external divider resistors set this bit to 0 bit4 BK Display blanking selec...

Page 462: ...t General purpose I O port Common output COM0 0 1 PICTL BLSEL reserved VE1 COM3 COM2 COM0 COM1 COM1 select bit General purpose I O port Common output COM1 0 1 COM2 select bit General purpose I O port Common output COM2 0 1 COM3 select bit General purpose I O port Common output COM3 0 1 V3 to V1 select bit General purpose I O port V3 to V1 dedicated pins VE1 0 1 Blinking interval select bit 0 5 s 1...

Page 463: ...g 1 0s causes the LCD to remain on for 0 5s and off for 0 5s the setting 0 5s causes it to remain on for 0 25s and off for 0 25s bit5 Reserve bit reserve bit always set 0 read value is 0 bit4 VE1 V3 to V1 select bit Selects the status of the V3 pin to V1 pin Setting the bit to 0 Causes the pins to function as general purpose I O ports Setting the bit to 1 Causes the pins to function as the V3 pin ...

Page 464: ...4 bit3 bit2 bit1 bit0 Initial value Address SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG09 SEG08 00000000B 0FC7H R W R W R W R W R W R W R W R W LCDCE4 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value Address SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 00000000B 0FC8H R W R W R W R W R W R W R W R W LCDCE5 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value Address SEG31 SEG30 SEG29 SEG28 00...

Page 465: ...ned on blink synchronously The setting of each blinking select bit remains in effect when the corresponding bit in display RAM holds 1 In product with single clock system the blinking function is disabled so LCDCB1 2has no effect LCDCB1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value Address S1C3 S1C2 S1C1 S1C0 S0C3 S0C2 S0C1 S0C0 00000000B 0FCBH R W R W R W R W R W R W R W R W LCDCB2 bit7 b...

Page 466: ...tting common outputs and bits used in display RAM Figure 24 5 1 shows how display RAM addresses are allocated for common output and segment output pins Figure 24 5 1 Display RAM and Common Segment Output Pins Note The number of segment output pins depends on each MCU series Address n bit3 bit2 bit1 bit0 SEG00 bit7 bit6 bit5 bit4 SEG01 n 1 bit3 bit2 bit1 bit0 SEG02 bit7 bit6 bit5 bit4 SEG03 n 2 bit...

Page 467: ...ion clock can be changed even during LCD display operation As the display may flicker when it is changed however you should always turn off the display temporarily for example using the blanking LCDCC BK 1 function in advance The display drive output is a 2 frame alternating waveform selected by bias and duty settings The COM2 and COM3 pin outputs in 1 2 duty mode and the COM3 pin output in 1 3 du...

Page 468: ...isplay operation must be stopped in advance The conditions under which the main clock timebase timer or subclock watch prescaler halts depend on the selected clock mode and standby mode The frame period is also affected if the timebase timer or watch prescaler is cleared depending on the setting of the frame period generation clock select bit LCDCC CSS LCD Drive Waveform Due to the characteristics...

Page 469: ...ither COM2 nor COM3 is used 1 2 Bias 1 2 Duty Output Waveform Example Those liquid crystal elements are turned ON for display which has the maximum potential difference between the common and segment outputs Figure 24 6 2 shows the output waveform when the contents of display RAM are those shown in Table 24 6 1 Unused Table 24 6 1 Sample Contents of Display RAM Segment Contents of Display RAM COM3...

Page 470: ...s SEG n V3 V2 V1 Vss SEG n 1 V3 V2 V1 Vss Potential difference between COM0 and SEG n V3 ON V2 Vss V2 V3 ON Potential difference between COM0 and SEG n 1 V3 ON V2 Vss V2 V3 ON Potential difference between COM1 and SEG n V3 ON V2 Vss V2 V3 ON Potential difference between COM1 and SEG n 1 V3 ON V2 Vss V2 V3 ON 1 frame 1 cycle V1 to V3 Voltages at V1 to V3 pins ...

Page 471: ...ut Waveform Example Those liquid crystal elements are turned ON for display which has the maximum potential difference between the common and segment outputs Figure 24 6 3 shows the output waveform when the contents of display RAM are those shown in Table 24 6 2 Unused Table 24 6 2 Sample Contents of Display RAM Segment Contents of Display RAM COM3 COM2 COM1 COM0 SEG n 1 0 0 SEG n 1 1 0 1 ...

Page 472: ...ween COM0 and SEG n 1 Potential difference between COM1 and SEG n 1 1 frame 1 cycle V1 to V3 Voltages at V1 to V3 pins V1 V3 V2 Vss V1 V3 V2 Vss V1 V3 V2 Vss V1 V2 Vss V1 V2 Vss V1 V3 V3 V2 Vss V1 V1 V2 V3 ON V2 Vss V1 V3 ON V1 V2 V3 ON V2 Vss V1 V3 ON V1 V2 V3 ON V2 Vss V1 V3 ON V1 V2 V3 ON Potential difference between COM2 and SEG n 1 V2 Vss V1 V1 V2 V3 ON V3 ON Potential difference between COM0...

Page 473: ...t Waveform Example Those liquid crystal elements are turned ON for display which has the maximum potential difference between the common and segment outputs Figure 24 6 4 shows the output waveform when the contents of display RAM are those shown in Table 24 6 3 Table 24 6 3 Sample Contents of Display RAM Segment Contents of Display RAM COM3 COM2 COM1 COM0 SEG n 0 1 0 0 SEG n 1 0 1 0 1 ...

Page 474: ...1 cycle V1 to V3 Voltages at V1 to V3 pins V1 V3 V2 Vss V1 V3 V2 Vss V1 V3 V2 Vss V1 V2 Vss V1 V2 Vss V1 V3 V3 V2 Vss V1 V1 V2 V3 ON V2 Vss V1 V3 ON V1 V2 V3 ON V2 Vss V1 V3 ON V1 V2 V3 ON V2 Vss V1 V3 ON V1 V2 V3 ON Potential difference between COM3 and SEG n 1 V2 Vss V1 V1 V2 V3 ON V3 ON Potential difference between COM0 and SEG n V2 Vss V1 V1 V2 V3 ON V3 ON V3 ON Potential difference between CO...

Page 475: ... 0 If the selected frame period generation clock halts during LCD display operation the AC waveform generator circuit also halts and therefore a DC voltage is applied to the liquid crystal elements In this case the LCD display operation must be stopped in advance The conditions under which the main clock timebase timer or subclock watch prescaler halts depend on the selected clock mode and standby...

Page 476: ...462 CHAPTER 24 LCD CONTROLLER ...

Page 477: ...unctions and operations of the low voltage detection reset circuit 25 1 Overview of Low voltage Detection Reset Circuit 25 2 Configuration of Low voltage Detection Reset Circuit 25 3 Pins of Low voltage Detection Reset Circuit 25 4 Operations of Low voltage Detection Reset Circuit ...

Page 478: ...ignal if the voltage drops below the detection voltage level available as an option to 5 V products only Low voltage Detection Reset Circuit This circuit monitors the power supply voltage and generates a reset signal if the voltage drops below the detection voltage level The circuit can be selected as an option to 5 V products only Refer to the data sheet for details of the electrical characterist...

Page 479: ...uration of Low voltage Detection Reset Circuit Figure 25 2 1 is a block diagram of the low voltage detection reset circuit Block Diagram of Low voltage Detection Reset Circuit Figure 25 2 1 Block Diagram of Low voltage Detection Reset Circuit Reset signal Vref VCC ...

Page 480: ... voltage detection reset circuit Pins Related to Low voltage Detection Reset Circuit VCC pin The low voltage detection reset circuit monitors the voltage at this pin VSS pin This pin is a GND pin serving as the reference for voltage detection RST pins The low voltage detection reset signal is output inside the microcontroller and to this pin ...

Page 481: ...tection voltage If the voltage is subsequently detected to have recovered the circuit outputs a reset signal for the duration of the oscillation stabilization wait time to cancel the reset For details on the electrical characteristics see the data sheet Figure 25 4 1 Operations of Low voltage Detection Reset Circuit Operations in Standby Mode The low voltage detection reset circuit remains operati...

Page 482: ...468 CHAPTER 25 LOW VOLTAGE DETECTION RESET CIRCUIT ...

Page 483: ...scribes the functions and operations of the clock supervisor 26 1 Overview of Clock Supervisor 26 2 Configuration of Clock Supervisor 26 3 Registers of Clock Supervisor 26 4 Operations of Clock Supervisor 26 5 Precautions when Using Clock Supervisor ...

Page 484: ...whether a reset was triggered by the clock supervisor A main clock oscillation halt is detected if the rising edge of the main clock is not detected for 4 CR clock cycles The clock supervisor may detect incorrectly if main clock is longer than 4 CR clock cycles A sub clock oscillation halt is detected if the rising edge of the sub clock is not detected for 32 CR clock cycles The clock supervisor m...

Page 485: ...f Clock Supervisor Figure 26 2 1 shows a block diagram of the clock supervisor Figure 26 2 1 Block Diagram of Clock Supervisor Control circuit Internal bus CSV control register CSVCR Main clock monitor Sub clock monitor Main clock From X0 X1 Sub clock From X0A X1A Enable Detect Enable Detect CR oscillator circuit Enable Main clock selector Sub clock selector 1 2 CR clock Select main clock Select s...

Page 486: ...ck after a clock halt is detected Main clock monitor This block monitors whether the main clock halts Sub clock monitor This block monitors whether the sub clock halts Main clock selector This block outputs the CR clock as the internal main clock upon detection of a main clock halt Sub clock selector This block outputs the clock obtained by dividing the CR clock as the internal sub clock upon dete...

Page 487: ...ock Supervisor Register Figure 26 3 1 shows the register of the clock supervisor Figure 26 3 1 Clock Supervisor Register Clock supervisor control register CSVCR bit 7 6 5 4 3 2 1 0 Address 000FEAH Reserved MM SM RCE MSVE SSVE SRST Reserved Initial value 00011100B R W R R R W R W R W R W R W R W Readable writable R Read only ...

Page 488: ...toring 1 Reset generation enable bit Disables reset generation Enables reset generation SRST 0 1 Reserved MM SM RCE MSVE SSVE SRST Reserved Assuming that a sub clock halt has been already detected at transition from main mode to sub mode Main clock monitoring enable bit Disables main clock monitoring MSVE Enables main clock monitoring CR clock oscillation enable bit Disables CR clock oscillation R...

Page 489: ...hat no sub clock oscillation halt has been detected Writing 1 to this bit does not affect the operation bit4 RCE CR clock oscillation enable bit This bit enables CR oscillation When set to 1 The bit enables oscillation When set to 0 The bit disables oscillation Before writing 0 to this bit make sure that the clock monitor function has been disabled with the MM and SM bits set to 0 bit3 MSVE Main c...

Page 490: ... reset is generated immediately if a sub clock halt is detected in main clock mode the sub clock switches to CR clock divided by two A reset can be generated when the device switches from main clock mode to sub clock mode with a sub clock oscillation halt detected by setting the SRST bit in the clock supervisor control register CSVCR Because the CR clock is used to detect whether the sub clock has...

Page 491: ...lation halt is detected during main clock operation the operating clock is switched to the CR clock and a reset is generated 4 If the main oscillation continues oscillation does not halt the device continues to run using the main clock 5 If an external reset occurs during the CR clock operation operation changes to the main clock However if the oscillation is halted at this time another CSV reset ...

Page 492: ...it CSVCR MM enables user programs to control the Fail Safe routine Figure 26 4 2 shows the example startup flowchart when using the clock supervisor Figure 26 4 2 Example Startup Flowchart when using the Clock Supervisor CSVCR MM 1 Yes Fail Safe routine PLL use prohibited No Yes NO Reset generated Use PLL Main routine main clock Main routine PLL clock ...

Page 493: ... Transition to CR clock mode Do not turn on the PLL after changing to CR clock mode As the frequency is below the lower limit for the input frequency of the PLL circuit the PLL operation will not be guaranteed Disabling the CR oscillation Do not use the CR oscillation enable bit CSVCR RCE to disable the CR oscillation during CR clock mode As this halts the internal clock it may result in deadlock ...

Page 494: ...480 CHAPTER 26 CLOCK SUPERVISOR ...

Page 495: ...es the functions and operations of the real time clock 27 1 Overview of Real time clock 27 2 Configuration of Real Time Clock 27 3 Registers of Real Time Clock 27 4 Real Time Clock Interrupt 27 5 Operation of the Real Time Clock 27 6 Notes on using RTC ...

Page 496: ...d so as to generate one second ticks to the real time clock In case there is deviation from one second due to the discrepancy induced by the oscillator Prescaler fine tuning circuit is provided to perform fine tuning Apart from 1Hz Prescaler can output 0 1Hz 64Hz and 1024Hz as well Through the output pin this set of frequencies works as test clocks The Real time clock have two different calibraion...

Page 497: ...omparator Month Comparator Day count and leap year logic Auto Calibration Control Circuit RTC Control Register Lower RTCCRL RTC Control Register Upper RTCCRH Minute Compare Register MICR Hour Compare Register HRCR Day Compare Register DYCR Month Compare Register MOCR Second Register SECR Minute Register MINR Hour Register HOUR Day of the Week Register DOWR Day Register DAYR Month Register MONR Yea...

Page 498: ...Upper RTCCRH IRQ11 1 Hz RTC Control Register Lower RTCCRL Comparator Comparator PAU CL PS INTS S2 S1 OE Frequency Fine tuning Register FFTR Second Register SECR Minute Register MINR Minute Compare Register MICR Hour Register HOUR Hour Compare Register HRCR Day of the Week Register DOWR Day Register DAYR Day Compare Register DYCR Month Register MONR Month Compare Register MOCR Year Register YEAR Da...

Page 499: ...e the day counter and the day compare register value Month Comparator This comparator is used to compare the month counter and the month compare register value Day count and leap year logic This logic features automatic leap year adjustment Auto calibration control circuit This circuit is used to measure the internal clock frequency and 1 HZ CALPL And the difference value will load to FFTR It also...

Page 500: ...ister is used to hold the minute information Hour Register HOUR This register is used to hold the hour information Day of the Week Register DOWR This register is used to hold the day of the week information Day Register DAYR This register is used to hold the day information Month Register MONR This register is used to hold the month information Year Register YEAR This register is used to hold the ...

Page 501: ... S1 OE 00X00000 B R W R W R W R0 WX R W R W R W R W Minute compare register MICR Address bit7 bit6 bit5 bit4 bit3 bit2 bit0 bit0 Initial value 0FF2H MICR MIC5 MIC4 MIC3 MIC2 MIC1 MIC0 00XXXXX XB R0 WX R0 WX R W R W R W R W R W R W Hour compare register HRCR Address bit7 bit6 bit5 bit4 bit3 bit2 bit0 bit0 Initial value 0FF3H HRCR HRC4 HRC3 HRC2 HRC1 HRC0 000XXXX XB R0 WX R0 WX R0 WX R W R W R W R W...

Page 502: ...W 1 DOW 0 00000XXX B R0 WX R0 WX R0 WX R0 WX R0 WX R W R W R W Day register DAYR Address bit7 bit6 bit5 bit4 bit3 bit2 bit0 bit0 Initial value 0FFAH DAYR DAY4 DAY3 DAY2 DAY1 DAY0 000XXXX XB R0 WX R0 WX R0 WX R W R W R W R W R W Month register MONR Address bit7 bit6 bit5 bit4 bit3 bit2 bit0 bit0 Initial value 0FFBH MONR MON 3 MON 2 MON 1 MON 0 0000XXX XB R0 WX R0 WX R0 WX R0 WX R W R W R W R W Year...

Page 503: ...489 CHAPTER 27 REAL TIME CLOCK 27 3 1 Real Time Clock Control Register Upper RTCCRH The Real Time Clock Control Register Upper is used to control the minute hour day and month alarm function ...

Page 504: ...ison MOC Month compare bit 0 Month compare register is masked 1 Enable month comparison MS Minute alarm interrupt request signal Read Write 0 No minute alarm interrupt request Clear this bit 1 Minute alarm interrupt request No effect HS Hour alarm interrupt request signal Read Write 0 No hour alarm interrupt request Clear this bit 1 Hour alarm interrupt request No effect DS Day alarm interrupt req...

Page 505: ...1 is always read Bit4 MS Minute alarm interrupt request signal When MC bit set to one the day comparison will be done between the compare register and the counter When they match MS will be set to one An interrupt request may be sent to the CPU which depends on the settings of compare bits and RTCCRL INTS Writing 0 clears this bit Writing 1 has no effect on this bit and does not alter the bit valu...

Page 506: ...ute counter for detecting alarm condition If there is match an interrupt request will be sent to the CPU When this bit set to 1 and RTCCRL INTS set to 1 an interrupt will be sent according to the table 1 5 2 When this bit is set to zero it disables the minute comparison Table 27 3 1 Functional Description of Each Bit of real time clock control register upper Bit name Function ...

Page 507: ...493 CHAPTER 27 REAL TIME CLOCK ...

Page 508: ... R W R W OE TPCLK output enable bit 0 Disable scaled clock signal to TPCLK 1 Enable scaled clock signal to TPCLK S2 S1 TPCLK output frequency selection bits 0 0 1 Hz 0 1 0 1 Hz 1 0 64 Hz 1 1 1024 Hz INTS Interrupt selection bit 0 Interrupt generated when any of the enabled comparison s matches 1 Interrupt generated when all of the enabled comparison s match PS Power save mode selection bit 0 Power...

Page 509: ... 1 the latched date and time are no longer secured Writing to MINR HOUR DAYR DOWR MONR YEAR FFTR will clear this bit to 0 Bit5 PS Power save mode selection bit Write 1 Select power save mode Write 0 Select non power save mode When this bit set to 1 the real time clock counters can still operate even the resource clock has stopped When this bit set to 1 all counters and registers except for this PS...

Page 510: ...r for detecting alarm condition In order to have proper operation minute compare value must be adequately set between 00H 0 minute and 3BH 59 minute inclusive If set CRTCRL PS to 1 The read value of MICR is indeterminate MICR Minute compare register Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial value 0FF2H MIC5 MIC4 MIC3 MIC2 MIC1 MIC0 00XXXXXXB R0 WX R0 WX R W R W R W R W R W R ...

Page 511: ...nter for detecting alarm condition In order to have proper operation hour compare value must be adequately set between 00H 0 hour and 17H 23 hour inclusive If set CRTCRL PS to 1 The read value of HRCR is indeterminate HRCR Hour compare register Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial value 0FF3H HRC4 HRC3 HRC2 HRC1 HRC0 000XXXXXB R0 WX R0 WX R0 WX R W R W R W R W R W R W Re...

Page 512: ... for detecting alarm condition In order to have proper operation day compare value must be adequately set between 00H day 1 and 1EH day 31 inclusive If set CRTCRL PS to 1 The read value of DYCR is indeterminate DYCR Day compare register Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial value 0FF4H DYC4 DYC3 DYC2 DYC1 DYC0 000XXXXXB R0 WX R0 WX R0 WX R W R W R W R W R W R W Readable a...

Page 513: ...counter for detecting alarm condition In order to have proper operation month compare value must be adequately set between 00H January and 0BH December inclusive If set CRTCRL PS to 1 The read value of MOCR is indeterminate MOCR Month compare register Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial value 0FF5H MOC3 MOC2 MOC1 MOC0 0000XXXXB R0 WX R0 WX R0 WX R0 WX R W R W R W R W R ...

Page 514: ...r operation second value must be adequately set between 00H 000000B or 0 second and 3BH 111011B or 59 second inclusive please note that only the latched value not the value being continuously updated in the counters is read from register while RTCCRL CL is equal to 1 SECR Real time clock second register Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial value 0FF6H SEC5 SEC4 SEC3 SEC2...

Page 515: ...r operation minute value must be adequately set between 00H 000000B or 0 minute and 3BH 111011B or 59 minute inclusive please note that only the latched value not the value being continuously updated in the counters is read from register while RTCCRL CL is equal to 1 MINR Real time clock minute register Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial value 0FF7H MIN5 MIN4 MIN3 MIN2...

Page 516: ...r operation hour value must be adequately set between 00H 000000B or 0 hour and 17H 10111B or 23 hour inclusive please note that only the latched value not the value being continuously updated in the counters is read from register while RTCCRL CL is equal to 1 HOUR Real time clock hour register Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial value 0FF8H HOU4 HOU3 HOU2 HOU1 HOU0 000...

Page 517: ...ad as 00000 In order to have proper operation day of the week value must be adequately set between 00H 000B or Sunday and 06H 110B or Saturday inclusive please note that only the latched value not the value being continuously updated in the counters is read from register while RTCCRL CL is equal to 1 DOWR Real time clock day of the week register Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bi...

Page 518: ...oper operation day value must be adequately set between 00H 000B or day1 and 1EH 11110B or day31 inclusive please note that only the latched value not the value being continuously updated in the counters is read from register while RTCCRL CL is equal to 1 DAYR Real time clock day register Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial value 0FFAH 000XXXXXB R0 WX R0 WX R0 WX R W R ...

Page 519: ... proper operation month value must be adequately set between 00H 0000B or January and 0BH 1011B or December inclusive please note that only the latched value not the value being continuously updated in the counters is read from register while RTCCRL CL is equal to 1 MONR Real time clock month register Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial value 0FFBH MON3 MON2 MON1 MON0 0...

Page 520: ...order to have proper operation year value must be adequately set between 00H 0000000B or Year 2000 and 7FH 1111111B or year 2127 inclusive please note that only the latched value not the value being continuously updated in the counters is read from register while RTCCRL CL is equal to 1 YEAR Real time clock year register Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial value 0FFCH Y...

Page 521: ...the tuning unit user must convert the offset value into 2 s complement format first and set it in the frequency fine tuning register Offset value can range from 128 80H to 127 7FH FFTR Frequency fine tuning register Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial value 0FFDH FFT7 FFT6 FFT5 FFT4 FFT3 FFT2 FFT1 FFT0 XXXXXXXXB R W R W R W R W R W R W R W R W Bit 7 Bit 6 Bit 5 Bit 4 Bi...

Page 522: ...e in frequency fine tuning register should be set to 01H so as to generate one second ticks Figure 27 3 18 subclock of Frequency 32769Hz If the sub clock is found to oscillate at 32 766 KHz the value in frequency fine tuning register should be set to FEH so as to generate one second ticks Figure 27 3 19 subclock of Frequency 32766Hz Notes Hardware writing can override software writing in FFTR 1 se...

Page 523: ...509 CHAPTER 27 REAL TIME CLOCK ...

Page 524: ...adable and writable Unused X Indeterminate CALIRQ Calibration completion bit 0 1 CALEN Read Write 0 Disable Auto Calibration 1 Start Auto Calibration interrupt enable Auto calibration completeion interrupt is masked Auto calibration completeion interrupt is not masked CALCP 0 1 Auto calibration has not start or not completed Auto calibration has completed Auto calibration status bit CALOF 0 1 no o...

Page 525: ... calibration status bit Write 0 The interrupt request has not been sent Write 1 The interrput requested has been sent after auto calibration is completed when calibraion completion interrupt function is enabled CALCR CALIRQ 1 Writing 0 to CALCP clear the bit writing 1 to it has no effect RMW read return 1 This bit is cleared by reset Bit1 CALOF Calibration Result overflow This bit is set to 1 when...

Page 526: ... counter RTCCRH MOS will be activated when RTCCRH MOC is 1 and month compare register matches month counter Apart from the enable bits and the matching s the generation of alarm interrupt request also depends on the RTCCRL INTS Besides the interrupt also can be generated by the completion underflow or overflow of auto calibraion Register and vector table for the real time clock interrupt Table 27 ...

Page 527: ...e and date When the counter latch bit RTCCRL CL is changed from 0 to 1 all counters s values at that moment will be latched to coreesponding counter registers When this bit is 1 the latched counter values are kept and can be read When 0 is written to RTCCRL CL the content of the latches will be no longer secured instead when this bit is 0 the latched counter values will being altered in line with ...

Page 528: ... or auto calibration function writing data to frequency fine tuning register FFTR can correct the clock error It can be expained by the operation of second counter and prescaler For example writing 8 H02 to FFTR prescaler value change to 7FFD by using the equation 7FFF offset value FFTR When the counter value matches the prescaler value the second counter increase one Prescaler value 7FFF offset v...

Page 529: ...TCCRH MOC DC HC MC are set to 1 the corresponding comparison will be continuously performed between the compare register and counter In case there is a match on that time information e g minute with enable bit 1 Alarm interrupt request bit of that time information will be set and it generates an alarm interrupt IRQ However if RTCCRL INTS is one alarm interrupt request bit of that time information ...

Page 530: ...mpare match 1 1 0 1 At least one match in minute day or month 1 1 1 0 At least one match in hour day or month 1 1 1 1 At least one match in minute hour day or month MOC DC HC MC Conditions for alarm interrupt IRQ is activated 0 0 0 0 All alarm functions are disabled 0 0 0 1 Minute compare match 0 0 1 0 Hour compare match 0 0 1 1 Minute and hour compare matches 0 1 0 0 Day compare match 0 1 0 1 Min...

Page 531: ...ource clock is stopped in power saving mode all user accessible registers except RTCCRL PS are not writable The read values are valid only for RTCCRL RTCCRH MOC DC HC MC MICR HOUR HRCR DYCR MOCR and FFTR Other registers are indeterminate Resource clock and subclock frequency There is an limitation on the frequency of resource clock operating in non power saving mode RTCCRL PS 0 As resource clock i...

Page 532: ...518 CHAPTER 27 REAL TIME CLOCK ...

Page 533: ...h memory 28 1 Overview of 256 Kbit Flash Memory 28 2 Sector Configuration of Flash Memory 28 3 Register of Flash Memory 28 4 Starting the Flash Memory Automatic Algorithm 28 5 Checking the Automatic Algorithm Execution Status 28 6 Details of Programming Erasing Flash Memory 28 7 Features of Flash Security ...

Page 534: ... and erased by the instructions from the CPU via the flash memory interface circuit you can efficiently reprogram update program code and data in flash memory with the device mounted on a circuit board Features of 256 Kbit Flash Memory Sector configuration 32K bytes 8 bits Automatic program algorithm Embedded Algorithm Detection of completion of programming erasing using the data polling or toggle...

Page 535: ... 256 Kbit flash memory The upper and lower addresses of each sector are given in the figure Figure 28 2 1 Sector Configuration of 256 Kbit Flash Memory Programmer addresses are corresponding to CPU addresses used when the parallel programmer programs data into flash memory These programmer addresses are used for the parallel programmer to program or erase data in flash memory FLASH memory CPU addr...

Page 536: ...522 CHAPTER 28 256 KBIT FLASH MEMORY ...

Page 537: ... 0072H RDYIRQ RDY Reserved IRQEN WRE Reserved 000X0000B R0 WX R0 WX R RM1 W R WX R W0 R W R W R W0 R W Readable writable Read value is the same as write value R RM1 W Readable writable Read value is different from write value 1 is read by read modify write instruction R WX Read only Readable writing has no effect on operation R W0 Reserved bit Write value is 0 read value is the same as write value...

Page 538: ...Initial value Reserved bit Write value is 0 read value is the same as write value R W0 Read only Readable writing has no effect on operation R WX Readable writable Read value is the same as write value R W Undefined bit The value read is always 0 Writing has no effect on the operation RDYIRQ IRQEN WRE RDY Re served WRE 0 1 Flash memory program erase enable bit Disables flash memory area programmin...

Page 539: ...this bit after for example inserting NOP twice after issuing the program erase command bit3 Reserved Reserved bit Be sure to set this bit to 0 bit2 IRQEN Flash memory program erase interrupt enable bit This bit enables or disables the generation of interrupt requests in response to the completion of flash memory programming erasing Setting the bit to 1 Causes an interrupt request to occur when the...

Page 540: ... the same value as RA and PA Example If RA C48EH U C If PA 1024H U 1 Table 28 4 1 Command Sequence Command sequence Bus write cycle 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus write cycle 5th bus write cycle 6th bus write cycle Address Data Address Data Address Data Address Data Address Data Address Data Read reset 1 FXXXH F0H 4 UAAAH AAH U554H 55H UAAAH F0H RA RD Write 4 U...

Page 541: ...mmands in the command sequence table The upper address U bits bits 15 to 12 used when commands are issued must have the same value as RA and PA from the first command on If the above measures are not followed commands are not recognized normally Execute a reset to initialize the command sequencer in the flash memory ...

Page 542: ...re sequence flags by read access to the address of each relevant sector in flash memory after setting a command sequence Note however that hardware sequence flags are output only for the bank on a command issued side Table 28 5 1 shows the bit allocation of the hardware sequence flags To know whether the automatic write or chip erase command is being executed or has been terminated check the hardw...

Page 543: ...rmal operation Programming Programming completed when write address has been specified DQ7 DATA 7 Toggle DATA 6 0 DATA 5 1 DATA 2 Chip erasing Erasing completed 0 1 Toggle Stop 0 1 Toggle Stop Abnormal operation Programming DQ7 Toggle 1 1 Chip erasing 0 Toggle 1 When the DQ5 flag is 1 execution time out the DQ2 flag toggles during continuous reading from the programming erasing sector but does not...

Page 544: ...ad accessed address to DQ7 At chip erasing When read access is made to the sector currently being erased during execution of the chip erase algorithm bit 7 of flash memory outputs 0 Bit 7 of flash memory outputs 1 upon completion of chip erasing Note Once the automatic algorithm has been started read access to the specified address is ignored Data reading is allowed after the data polling flag DQ7...

Page 545: ...rite algorithm or chip erase algorithm the flash memory toggles the output between 1 and 0 at each read access When read access is made continuously after the automatic write algorithm or chip erase algorithm is terminated the flash memory outputs bit 6 DATA 6 of the value read from the read address at each read access Table 28 5 5 State Transition of Toggle Bit Flag During Normal Operation Operat...

Page 546: ...xecution time out flag DQ5 outputs 1 it indicates that programming has failed if the automatic algorithm is still running for the data polling or toggle bit function If an attempt is made to write 1 to a flash memory address holding 0 for example the flash memory is locked preventing the automatic algorithm from being terminated and valid data from being output from the data polling flag DQ7 As th...

Page 547: ...her sectors At chip erasing When read access is made continuously during execution of the chip erase algorithm the flash memory toggles the output between 1 and 0 at each read access When read access is made continuously after the chip erase algorithm is terminated the flash memory outputs bit 2 DATA 2 of the value read from the read address at each read access Table 28 5 9 State Transition of Tog...

Page 548: ...tic algorithm can be invoked by writing the read reset program and chip erase command sequence to flash memory from the CPU Writing command sequence to flash memory from the CPU must always be performed continuously The termination of the automatic algorithm can be checked by the data polling function After the automatic algorithm terminates normally the flash memory returns to the read reset stat...

Page 549: ...volves a single bus operation and the other involves four bus operations which are essentially the same Since the read reset state is the initial state of flash memory the flash memory always enters this state after the power is turned on and at the normal termination of a command The read reset state is also described as the wait state for command input In the read reset state read access to flas...

Page 550: ...on time out flag DQ5 detects an error to indicate that the specified programming time has been exceeded When data is read in the read reset state the bit data remains 0 To return the bit data from 0 to 1 erase flash memory All commands are ignored during automatic programming If a hardware reset occurs during programming the data being programmed to the current address is not guaranteed Retry from...

Page 551: ...rnal address Programming command sequence 1 UAAA AA 2 U554 55 3 UAAA A0 4 Write address Write data Next address Read internal address FSR WRE bit1 Writable flash memory Data polling DQ7 Data polling DQ7 Data Data Timing limit DQ5 1 End of writing 0 Last address YES NO FSR WRE bit1 Write disable flash memory Write error Data Data ...

Page 552: ...mmand sequence table continuously from the CPU to flash memory The chip erase command is executed in six bus operations Chip erasing is started upon completion of the sixth programming cycle Before chip erasing the user need not perform programming into flash memory During execution of the automatic erase algorithm flash memory automatically programs 0 before erasing all cells automatically Notes ...

Page 553: ...write access to flash memory from any external pin Once flash memory has been protected the function cannot be unlocked until the chip erase command is executed Note that only addresses 5554H and 2AAAH can be read as exceptions It is advisable to code the protection code at the end of flash programming This is to avoid unnecessary protection during programming Once flash memory has been protected ...

Page 554: ...540 CHAPTER 28 256 KBIT FLASH MEMORY ...

Page 555: ...ON This chapter describes the example of a serial programming connection 29 1 Basic Configuration of MB95170J Serial Programming Connection 29 2 Example of Serial Programming Connection 29 3 Example of Minimum Connection to Flash Microcomputer Programmer ...

Page 556: ...d is used for Fujitsu standard serial onboard programming Figure 29 1 1 shows the basic configuration of MB95170J serial programming connection Figure 29 1 1 Basic Configuration of MB95170J Serial Programming Connection Note For the function and operation method of the AF220 AF210 AF120 AF110 flash microcomputer programmer and the general purpose common cable AZ210 and connector contact Yokogawa D...

Page 557: ...mode is the oscillator frequency divided by two Note that a 1MHz or higher oscillator frequency must be input when performing serial writing RST Reset pin P10 UI0 EC0 Serial data input pin Setting P10 UI0 Low specifies that serial write mode uses clock synchronous communications As this low input is handled by the TTXD pin of the flash microcomputer programmer you do not need to provide a pull dow...

Page 558: ...rocomputer Maximum serial clock frequency that can be set on the AF220 AF210 AF120 and AF110 Maximum serial clock frequency that can be set on the AF200 at 4MHz 500kHz 500kHz 500kHz at 8MHz 1MHz 850kHz 500kHz at 10MHz 1 25MHz 1 25MHz 500kHz Table 29 1 2 System Configuration of the Flash Microcomputer Program Yokogawa Digital Computer Co Ltd Type Function Main unit AF220 AC4P Model with built in Et...

Page 559: ...nsfer starts Setting P10 UI0 Low in this way specifies that serial write mode uses clock synchronous communications Note that a user power supply is required for serial writing Figure 29 2 1 Example of MB95170J Serial Programming Connection Vss Vcc GND Connector DX10 28S AF220 AF210 AF120 AF110 flash microcomputer programmer MB95F108A H 7 8 14 15 21 22 1 28 User system Pins 3 4 9 11 12 16 17 18 20...

Page 560: ...s required if you want to disconnect from the user circuit during serial writing The TICS signal of the flash microcomputer programmer can be used to disconnect from the user circuit during serial writing See the connection example in Figure 29 1 2 for details Figure 29 2 2 Control Circuit Only connect to the AF220 AF210 AF120 or AF110 while the user power supply is turned off Note The pull up and...

Page 561: ...al write mode MOD H P12 H P13 L Example of Minimum Connection to Flash Microcomputer Programmer Figure 29 3 1 shows an example of the minimum possible connection to the flash microcomputer programmer The TTXD pin on the flash microcomputer programmer is connected to P10 UI0 and outputs low until data transfer starts Setting P10 UI0 Low in this way specifies that serial write mode uses clock synchr...

Page 562: ...le in Figure 29 2 1 for details Only connect to the AF220 AF210 AF120 or AF110 while the user power supply is turned off Vss GND Connector DX10 28S AF220 AF210 AF120 AF110 flash microcomputer programmer MB95F108A H 7 8 14 15 21 22 1 28 User system Pin 1 Pin 28 Pin 15 Pin 14 Connector manufactured by Hirose Electric Co Ltd pin alignment DX10 28S DX10 28S Right angle type User powersupply P10 UI0 TT...

Page 563: ...ll down resistances in the above example connection are examples only and may be adjusted to suit your system If variation in the input level to the MOD pin is possible due to noise or other factors it is also recommended that you use a capacitor or other method to minimize noise ...

Page 564: ...550 CHAPTER 29 EXAMPLE OF SERIAL PROGRAMMING CONNECTION ...

Page 565: ... status instruction overview mask option and writing to Flash microcomputer using parallel writer APPENDIX A I O Map APPENDIX B Table of Interrupt Causes APPENDIX C Instruction Overview APPENDIX D Mask Option APPENDIX E Writing to Flash Microcontroller Using Parallel Writer ...

Page 566: ...imebase timer control register R W 00000000B 000BH WPCR Watch prescaler control register R W 00000000B 000CH WDTC Watchdog timer control register R W 00000000B 000DH HWDC Hardware watchdog timer control register R W 00000000B 000EH to 0011H Vacancy 0012H PDR4 Port 4 data register R W 00000000B 0013H DDR4 Port 4 direction register R W 00000000B 0014H PDR5 Port 5 data register R W 00000000B 0015H DD...

Page 567: ... control register upper ch 6 R W 00000000B 003FH PCNTL6 16 bit PPG status control register lower ch 6 R W 00000000B 0040H PCNTH7 16 bit PPG status control register upper ch 7 R W 00000000B 0041H PCNTL7 16 bit PPG status control register lower ch 7 R W 00000000B 0042H PCNTH0 16 bit PPG status control register upper ch 0 R W 00000000B 0043H PCNTL0 16 bit PPG status control register lower ch 0 R W 00...

Page 568: ...C address register ch 0 R W 00000000B 0065H ICCR0 I2C clock control register ch 0 R W 00000000B 0066H to 006BH Vacancy 006CH ADC1 10 bit A D converter control register 1 R W 00000000B 006DH ADC2 10 bit A D converter control register 2 R W 00000000B 006EH ADDH 10 bit A D converter data register upper byte R W 00000000B 006FH ADDL 10 bit A D converter data register lower byte R W 00000000B 0070H WCS...

Page 569: ...gister ch 0 R W 00000000B 0F96H TMCR0 8 16 bit composite timer 00 01 timer mode control register ch 0 R W 00000000B 0F97H T11CR0 8 16 bit composite timer 11 control status register 0 ch 1 R W 00000000B 0F98H T10CR0 8 16 bit composite timer 10 control status register 0 ch 1 R W 00000000B 0F99H T11DR 8 16 bit composite timer 11 data register ch 1 R W 00000000B 0F9AH T10DR 8 16 bit composite timer 10...

Page 570: ...gister lower ch 2 R W 11111111B 0FBAH PDUTH2 16 bit PPG duty setting buffer register upper ch 2 R W 11111111B 0FBBH PDUTL2 16 bit PPG duty setting buffer register lower ch 2 R W 11111111B 0FBCH Vacancy 0FBDH 0FBEH PSSR0 UART SIO prescaler select register ch 0 R W 00000000B 0FBFH BRSR0 UART SIO baud rate setting register ch 0 R W 00000000B 0FC0H to 0FC2H Vacancy 0FC3H AIDRL A D input disable regist...

Page 571: ...ute compare register R W 00xxxxxxB 0FF3H HRCR Hour compare register R W 000xxxxxB 0FF4H DYCR Day compare register R W 0000xxxxB 0FF5H MOCR Month compare register R W 0000xxxxB 0FF6H SECR Second register R W 00xxxxxxB 0FF7H MINR Minute register R W 00xxxxxxB 0FF8H HOUR Hour register R W 000xxxxxB 0FF9H DOWR Day of the week register R W 00000xxxB 0FFAH DAYR Day register R W 000xxxxxB 0FFBH MONR Mont...

Page 572: ...RQ4 FFF2H FFF3H L04 1 0 8 16 bit composite timer ch 0 lower IRQ5 FFF0H FFF1H L05 1 0 8 16 bit composite timer ch 0 upper IRQ6 FFEEH FFEFH L06 1 0 Not used IRQ7 FFECH FFEDH L07 1 0 Not used IRQ8 FFEAH FFEBH L08 1 0 Not used IRQ9 FFE8H FFE9H L09 1 0 Not used IRQ10 FFE6H FFE7H L10 1 0 RTC IRQ11 FFE4H FFE5H L11 1 0 Not used IRQ12 FFE2H FFE3H L12 1 0 Not used IRQ13 FFE0H FFE1H L13 1 0 8 16 bit composit...

Page 573: ...ction Code and Instruction MapInstruction Code and Instruction Map The instruction is classified into following four types forwarding system operation system branch system and others There are various methods of addressing and ten kinds of addressing can be selected by the selection and the operand specification of the instruction This provides with the bit operation instruction and can operate th...

Page 574: ...ulator Whether 8 bit length or 16 bit length is decided by the instruction used TH Upper 8 bit of temporary accumulator 8 bit length TL Lower 8 bit of temporary accumulator 8 bit length IX Index register 16 bit length EP Extra pointer 16 bit length PC Program counter 16 bit length SP Stack pointer 16 bit length PS Program status 16 bit length dr Either of accumulator or index register 16 bit lengt...

Page 575: ...tion It shows the operations for the instruction TL TH AH They show the change auto forwarding from A to T in the content when each TL TH and AH instruction is executed The sign in the column indicates the followings respectively No change dH upper 8 bits of the data described in operation AL and AH the contents become those of the immediately preceding instruction s AL and AH 00 Become 00 N Z V C...

Page 576: ...ress is 00H to 7FH it is accessed into 0000H to 007FH Moreover when the operand address is 80H to FFH the access can be mapped in 0080H to 047FH by setting of direct bank pointer DP Figure C 1 1 shows an example Figure C 1 1 Example of Direct Addressing Extended addressing This is used when the area of the entire 64 K bytes is accessed by addressing shown ext in the instruction table In this addre...

Page 577: ...ended and added to IX index register to the resulting address Figure C 1 4 shows an example Figure C 1 4 Example of Index Addressing Pointer addressing This is used when the area of the entire 64 K bytes is accessed by addressing shown EP in the instruction table In this addressing the content of EP extra pointer is assumed to be an address Figure C 1 5 shows an example Figure C 1 5 Example of Poi...

Page 578: ...s registered in the table with the addressing shown vct in the instruction table In this addressing information on vct is contained in the operation code and the address of the table is created using the combinations shown in Table C 1 1 Figure C 1 8 shows an example Figure C 1 8 Example of Vector Addressing 0 1 5 6H MOV A R 6 A BH A A BH 0 1 0 1 0B RP MOV A 56H 5 6H A Table C 1 1 Vector Table Add...

Page 579: ...1 9 Example of Relative Addressing In this example by jumping to the address where the operation code of BNE is stored it results in an infinite loop Inherent addressing This is used when doing the operation decided by the operation code with the addressing that does not have the operand in the instruction table In this addressing the operation depends on each instruction Figure C 1 10 shows an ex...

Page 580: ...shows a summary of the instruction Figure C 2 2 MOVW A PC When this instruction is executed the content of A reaches the same value as the address where the following instruction is stored rather than the address where operation code of this instruction is stored Therefore in Figure C 2 2 the value 1234H stored in A corresponds to the address where the following operation code of MOVW A PC is stor...

Page 581: ...executed A becomes the address that follows the address where the operation code of XCHW A PC is stored This instruction is effective especially when it is used in the main routine to specify a table for use in a subroutine Figure C 2 5 shows a summary of the instruction Figure C 2 5 XCHW A PC When this instruction is executed the content of A reaches the same value as the address where the follow...

Page 582: ...LV 3 After the CALLV vct instruction is executed the contents of PC saved on the stack area are the address of the operation code of the next instruction rather than the address of the operation code of CALLV vct Accordingly Figure C 2 7 shows that the value saved in the stack 1232H and 1233H is 5679H which is the address of the operation code of the instruction that follows CALLV vct return addre...

Page 583: ...e C 2 1 Vector Table Vector use call instruction Vector table address Upper Lower CALLV 7 FFCEH FFCFH CALLV 6 FFCCH FFCDH CALLV 5 FFCAH FFCBH CALLV 4 FFC8H FFC9H CALLV 3 FFC6H FFC7H CALLV 2 FFC4H FFC5H CALLV 1 FFC2H FFC3H CALLV 0 FFC0H FFC1H ...

Page 584: ...n a normal read operation and a read modify write operation I O ports during a bit manipulation From some I O ports an I O pin value is read during a normal read operation while a port data register value is read during a bit manipulation This prevents the other port data register bits from being changed accidentally regardless of the I O directions and states of the pins Interrupt request flag bi...

Page 585: ...f 1 AL D6 19 MOVW ext A 5 3 ext AH ext 1 AL D4 20 MOVW EP A 3 1 EP AH EP 1 AL D7 21 MOVW EP A 1 1 EP A E3 22 MOVW A d16 3 3 A d16 AL AH dH E4 23 MOVW A dir 4 2 AH dir AL dir 1 AL AH dH C5 24 MOVW A IX off 4 2 AH IX off AL IX off 1 AL AH dH C6 25 MOVW A ext 5 3 AH ext AL ext 1 AL AH dH C4 26 MOVW A A 3 1 AH A AL A 1 AL AH dH 93 27 MOVW A EP 3 1 AH EP AL EP 1 AL AH dH C7 28 MOVW A EP 1 1 A EP dH F3 ...

Page 586: ...A T A C dH 33 14 SUBC A 1 1 AL TL AL C 32 15 INC Ri 3 1 Ri Ri 1 C8 to CF 16 INCW EP 1 1 EP EP 1 C3 17 INCW IX 1 1 IX IX 1 C2 18 INCW A 1 1 A A 1 dH C0 19 DEC Ri 3 1 Ri Ri 1 D8 to DF 20 DECW EP 1 1 EP EP 1 D3 21 DECW IX 1 1 IX IX 1 D2 22 DECW A 1 1 A A 1 dH D0 23 MULU A 8 1 A AL TL dH 01 24 DIVU A 17 1 A T A MOD T dL dH dH 11 25 ANDW A 1 1 A A T dH R 63 26 ORW A 1 1 A A T dH R 73 27 XORW A 1 1 A A ...

Page 587: ...h 2 4 BNC BHS rel at branch 4 2 ifC 0thenPC PC rel F8 BNC BHS rel at no branch 2 5 BN rel at branch 4 2 ifN 1thenPC PC rel FB BN rel at no branch 2 6 BP rel at branch 4 2 ifN 0thenPC PC rel FA BP rel at no branch 2 7 BLT rel at branch 4 2 ifV N 1thenPC PC rel FF BLT rel at no branch 2 8 BGE rel at branch 4 2 ifV N 0thenPC PC rel FE BGE rel at no branch 2 9 BBC dir b rel 5 3 if dir b 0thenPC PC rel...

Page 588: ...OVW A PS MOVW PS A OR A ORW A OR A d8 OR A dir OR A IX d OR A EP OR A R0 OR A R1 OR A R2 OR A R3 OR A R4 OR A R5 OR A R6 OR A R7 CLRI CLRC MOV A T MOVW A T DAA MOV dir d8 MOV IX d d8 MOV EP d8 MOV R0 d8 MOV R1 d8 MOV R2 d8 MOV R3 d8 MOV R4 d8 MOV R5 d8 MOV R6 d8 MOV R7 d8 SETI SETC MOV A A MOVW A A DAS CMP dir d8 CMP IX d d8 CMP EP d8 CMP R0 d8 CMP R1 d8 CMP R2 d8 CMP R3 d8 CMP R4 d8 CMP R5 d8 CMP...

Page 589: ...70J series is shown in Table D 1 Mask Option List Table D 1 Mask Option List No Part number MB95F176JS MB95F176JW Specifying procedure Setting disabled Setting disabled 1 Clock mode select Single system clock mode Dual system clock mode Single system clock mode Dual system clock mode ...

Page 590: ...d for CPU access and programming by the parallel programmer as follows How to Write 1 Set the type code of the parallel programmer to 17222 2 Load program data to programmer addresses 0000H to 7FFFH 3 Programmed by parallel programmer Table E 1 Parallel Writer and Adaptor Package Compatible adaptor model Parallel writer FPT 64P M23 TBD TBD FPT 64P M24 TBD TBD MB95F176JS MB95F176JW 32 Kbytes Progra...

Page 591: ...tus register 524 H HOUR Hour Register 502 HRCR Hour Compare Register 497 HWDC Hardware Watchdog Timer Control Register186 187 I IAAR0 I2C address register ch0 389 IAAR1 I2 C address register ch1 389 IBCR00 I2 C bus control register 0 ch0 378 IBCR01 I2C bus control register 0 ch1 378 IBCR10 I2 C bus control register 1 ch0 378 IBCR11 I2 C bus control register 1 ch1 378 IBSR0 I2C bus status register ...

Page 592: ...ing buffer register upper ch 6282 PCSRH7 16 bit PPG cycle setting buffer register upper ch 7282 PCSRL0 16 bit PPG cycle setting buffer register lower ch0285 PCSRL1 16 bit PPG cycle setting buffer register lower ch1285 PCSRL2 16 bit PPG cycle setting buffer register lower ch 2282 PCSRL3 16 bit PPG cycle setting buffer register lower ch 3282 PCSRL4 16 bit PPG cycle setting buffer register lower ch 4...

Page 593: ... up register 102 R RDR0 UART SIO serial input data register ch0 340 RSSR Reset source register 88 RTCCRHReal Time Clock Control Register Upper 490 RTCCRL Real Time Clock Control Register Lower 494 S SECR Second Register 500 SMC10 UART SIO serial mode control register 1 ch0334 SMC20 UART SIO serial mode control register 2 ch0336 SSR0 UART SIO serial status and data register ch0338 STBC Standby cont...

Page 594: ...er ch1226 WRARH2Wild register address setup register upper ch2226 WRARL0Wild register address setup register lower ch0226 WRARL1Wild register address setup register lower ch1226 WRARL2Wild register address setup register lower ch2226 WRDR0 Wild register data setup register ch0 225 WRDR1 Wild register data setup register ch1 225 WRDR2 Wild register data setup register ch2 225 WREN Wild register add...

Page 595: ...581 INDEX INDEX The index follows on the next page This is listed in alphabetic order ...

Page 596: ...582 INDEX Index ...

Page 597: ...583 INDEX ...

Page 598: ...mode pin 30 P PPG0 16 bit PPG output pin ch0 279 S SCL0 I2 C clock input output pin ch0 375 SDA0 I2C data line pin ch0 375 SEG00 LCD segment output 0 439 SEG01 LCD segment output 1 439 SEG02 LCD segment output 2 439 SEG03 LCD segment output 3 439 SEG04 LCD segment output 4 439 SEG05 LCD segment output 5 439 SEG06 LCD segment output 6 439 SEG07 LCD segment output 7 439 SEG08 LCD segment output 8 43...

Page 599: ...585 Pin Function Index V2 LCD power supply driving pin 2 439 V3 LCD power supply driving pin 3 439 ...

Page 600: ...586 Pin Function Index ...

Page 601: ...0 FUJITSU SEMICONDUCTOR CONTROLLER MANUAL F2 MC 8FX 8 BIT MICROCONTROLLER MB95170J Series HARDWARE MANUAL March 2007 the first edition Published FUJITSU LIMITED Electronic Devices Edited Business Promotion Dept ...

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