Fujitsu F2 MC-8FX Family, Hardware Manual

Page: 493 / 602

479
CHAPTER 26 CLOCK SUPERVISOR
26.5 Precautions when Using Clock Supervisor
Take note of the following points when using the clock supervisor.
■
Precautions when using the Clock Supervisor
●
Operation of the clock supervisor at power on
When the power is turned on, the clock supervisor starts monitoring after the oscillation stabilization wait
time for the main clock has elapsed. Therefore, unless the operation continues for longer than the
oscillation stabilization wait time for the main clock, the clock supervisor will not operate.
●
Transition to CR clock mode
Do not turn on the PLL after changing to CR clock mode.
As the frequency is below the lower limit for the input frequency of the PLL circuit, the PLL operation will
not be guaranteed.
●
Disabling the CR oscillation
Do not use the CR oscillation enable bit (CSVCR:RCE) to disable the CR oscillation during CR clock
mode.
As this halts the internal clock, it may result in deadlock.
●
Initializing the main clock halt detection bit
The main clock halt detection bit (CSVCR:MM) is initialized by a power-on reset nor external reset only.
The bit is not initialized by neither a watchdog reset, software reset, nor CSV reset. Accordingly, the device
remains in CR clock mode if one of these resets occurs during CR clock mode.