Fujitsu F2 MC-8FX Family, Hardware Manual

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CHAPTER 26 CLOCK SUPERVISOR
26.1 Overview of Clock Supervisor
The clock supervisor prevents the situation which is out of control, when main clock
and sub clock (only on dual clock products) oscillations have halted. This function
switches to an CR clock generated in internal CR oscillator circuit, if main clock and sub
clock oscillations have halted. (this feature is optional to 5-V products).
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Overview of Clock Supervisor
• The clock supervisor monitors the main clock and sub clock oscillations and generates an internal reset
if it detects that the oscillation has halted. In this case, the clock supervisor switches to the internal CR
clock (The clock frequency of the sub clock is equal to the CR clock frequency divided by 2).
The reset source register (RSRR) can be used to determine whether a reset was triggered by the clock
supervisor.
• A main clock oscillation halt is detected if the rising edge of the main clock is not detected for 4 CR
clock cycles. The clock supervisor may detect incorrectly, if main clock is longer than 4 CR clock
cycles.
• A sub clock oscillation halt is detected if the rising edge of the sub clock is not detected for 32 CR clock
cycles. The clock supervisor may detect incorrectly, if sub clock is longer than 32 CR clock cycles.
• The clock supervisor can prohibit to monitor the main clock and sub clock respectively.
• If the sub clock is halted in the main clock mode, a reset does not occur immediately, but does occur
after switching to the sub clock mode.
Setting registers enable to prohibit the reset output.
• While the clock stops in main clock and sub clock stop modes, clock monitoring is disabled.
• This function can be selected as an option on 5-V products only.
Note:
Refer to the data sheet for the period and other details about the CR clock.