Fujitsu F2 MC-8FX Family, Hardware Manual

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55
CHAPTER 6 CLOCK CONTROLLER
Table 6.4-1 Functions of Bits in PLL Control Register (PLLC)
Bit name Function
bit7
MPEN:
Main PLL clock
oscillation enable bit
Enables or disables the oscillation of the main PLL clock in main clock mode or timebase timer
mode.
When set to "1": the bit enables main PLL clock oscillation.
When set to "0": the bit disables main PLL clock oscillation.
In main PLL clock mode, the main PLL clock oscillates regardless of the value of this bit either in
the RUN state or in sleep mode.
bit6
bit5
MPMC1, MPMC0:
Main PLL clock
multiplier setting bits
Set the multiplier for the main PLL clock.
Note: The value of these bits can be changed only when the main PLL clock is stopped.
Therefore, do not attempt to update the bits with the PLL clock oscillation enable bit
(MPEN) is set to "1" or with the clock mode selection bits in the system clock control
register (SYCC: SCS1, 0) are set to "11". (It is however possible to set these bits at the
same time as setting MPEN to "1".)
bit4
MPRDY:
Main PLL clock
oscillation stability bit
Indicates whether main PLL clock oscillation has become stable.
• When set to "1", the MPRDY bit indicates that the oscillation stabilization wait time for the main
PLL clock has passed.
• When set to "0", the MPRDY bit indicates that the clock controller is in the main PLL clock
oscillation stabilization wait state or that main PLL clock oscillation has been stopped.
This bit is read-only; any value attempted to be written is meaningless and has no effect on the
operation.
bit3
to
bit0
Unused bits
When read, these bits always return "0". These are unused bits.
When write,these bits should be written by "0".
MPMC1 MPMC0 Main PLL clock multiplier setting bits
0 0 Main clock x 1
0 1 Main clock x 2
1 0 Main clock x 2.5
1 1 Setting prohibited