Fujitsu F2 MC-8FX Family, Hardware Manual

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79
CHAPTER 6 CLOCK CONTROLLER
6.11 Configuration of Prescaler
Figure 6.11-1 is a block diagram of the prescaler.
■
Prescaler Block Diagram
Figure 6.11-1 Prescaler Block Diagram
• 5-bit counter
The machine clock (MCLK) is counted by a 5-bit counter and the count value is output to the output
control circuit.
• Output control circuit
Based on the 5-bit counter value, this circuit supplies clocks generated by frequency-dividing the
machine clock (MCLK) by 2, 4, 8, 16, or 32 to individual peripheral resources. The circuit also buffers
the clock from the timebase timer (2
7
/F
CH
and 2
8
/F
CH
) and supplies it to the peripheral resources.
■
Input Clock
The prescaler uses the machine clock or the clock output from the timebase timer as the input clock.
■
Output Clock
The prescaler supplies clocks to the 8/10-bit composite timer, 16-bit PPG timer, UART/SIO dedicated baud
rate generator, and 10-bit A/D converter.
MCLK: Machine clock (internal operating frequency)
Prescaler
2
7
/F
CH
Output
control circuit
2
8
/F
CH
MCLK (machine clock)
From
timebase
timer
Count
clock
source
To
individual
peripheral
resources
5-bit
counter
2
7
/F
CH
2/MCLK
2
8
/F
CH
4/MCLK
8/MCLK
16/MCLK
32/MCLK
Counter value