Debug Module
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
31-39
higher than the nonmaskable level-7 interrupt request. As with all interrupts, it is made pending until the
processor reaches a sample point, which occurs once per instruction. Again, the hardware forces the PC
breakpoint to occur before the targeted instruction executes and is precise. This is possible because the PC
breakpoint is enabled when interrupt sampling occurs. For address and data breakpoints, reporting is
considered imprecise, because several instructions may execute after the triggering address or data is
detected.
As soon as the debug interrupt is recognized, the processor aborts execution and initiates exception
processing. This event is signaled externally by the assertion of a unique PST value (PST = 0xD) for
multiple cycles. The core enters emulator mode when exception processing begins. After the standard
8-byte exception stack is created, the processor fetches a unique exception vector, 12, from the vector
table.Refer to the
ColdFire Programmer’s Reference Manual
. for more information.
Execution continues at the instruction address in the vector corresponding to the debug interrupt. All
interrupts are ignored while the processor is in emulator mode. The debug interrupt handler can use
supervisor instructions to save the necessary context, such as the state of all program-visible registers into
a reserved memory area.
When debug interrupt operations complete, the RTE instruction executes and the processor exits emulator
mode. After the debug interrupt handler completes execution, the external development system can use
BDM commands to read the reserved memory locations.
In revision B/B+, the hardware inhibits generation of another debug interrupt during the first instruction
after the RTE exits emulator mode. This behavior is consistent with the logic involving trace mode where
the first instruction executes before another trace exception is generated. Thus, all hardware breakpoints
are disabled until the first instruction after the RTE completes execution, regardless of the programmed
trigger response.
31.4.2.2
Emulator Mode
Emulator mode facilitates non-intrusive emulator functionality. This mode can be entered in three different
ways:
•
Setting CSR[EMU] forces the processor into emulator mode. EMU is examined only if RSTI is
negated and the processor begins reset exception processing. It can be set while the processor is
halted before reset exception processing begins. See
.
•
A debug interrupt always puts the processor in emulation mode when debug interrupt exception
processing begins.
•
Setting CSR[TRC] forces the processor into emulation mode when trace exception processing
begins.
While operating in emulation mode, the processor exhibits the following properties:
•
All interrupts are ignored, including level-7 interrupts.
•
If CSR[MAP] is set, all caching of memory and the SRAM module are disabled. All memory
accesses are forced into a specially mapped address space signaled by TT equals 0x2,
TM equals 0x5, or 0x6. This includes stack frame writes and vector fetch for the exception that
forced entry into this mode.
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International
Trade
Commission,
BGA-packaged
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MCF52235CVM60
