Fast Ethernet Controller (FEC)
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
18-32
Freescale Semiconductor
18.5.4.9
Receive Control Register (RCR)
The RCR is programmed by the user. The RCR controls the operational mode of the receive block and
should be written only when ECR[ETHER_EN] equals 0 (initialization time).
Figure 18-12. Receive Control Register (RCR)
IPSBAR
Offset: 0x1084 (RCR)
Access: User read/write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
0
0
0
0
MAX_FL
W
Reset
0
0
0
0
0
1
0
1
1
1
1
0
1
1
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
0
0
FCE
BC_R
EJ
PRO
M
MII_M
ODE
DRT LOOP
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Table 18-21. RCR Field Descriptions
Field
Description
31–27
Reserved, should be cleared.
26–16
MAX_FL
Maximum frame length. Resets to decimal 1518. Length is measured starting at DA and includes
the CRC at the end of the frame. Transmit frames longer than MAX_FL causes the BABT interrupt
to occur. Receive Frames longer than MAX_FL causes the BABR interrupt to occur and sets the
LG bit in the end of frame receive buffer descriptor. The recommended default value to be
programmed by the user is 1518 or 1522 (if VLAN Tags are supported).
15–6
Reserved, should be cleared.
5
FCE
Flow control enable. If asserted, the receiver detects PAUSE frames. Upon PAUSE frame
detection, the transmitter stops transmitting data frames for a given duration.
4
BC_REJ
Broadcast frame reject. If asserted, frames with DA (destination address) = FF_FF_FF_FF_FF_FF
are be rejected unless the PROM bit is set. If BC_REJ and PROM = 1, frames with broadcast DA
are accepted and the M (MISS) bit is set in the receive buffer descriptor.
3
PROM
Promiscuous mode. All frames are accepted regardless of address matching.
2
MII_MODE
Media independent interface mode. Selects external interface mode. Setting this bit to one selects
MII mode, setting this bit equal to zero selects 7-wire mode (used only for serial 10 Mbps). This bit
controls the interface mode for transmit and receive blocks.
1
DRT
Disable receive on transmit.
0 Receive path operates independently of transmit (use for full duplex or to monitor transmit
activity in half duplex mode).
1 Disable reception of frames while transmitting (normally used for half duplex mode).
0
LOOP
Internal loopback. If set, transmitted frames are looped back internal to the device and the transmit
output signals are not asserted. The system clock is substituted for the ETXCLK when LOOP is
asserted. DRT must be set to zero when asserting LOOP.
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
