Ethernet Physical Transceiver (EPHY)
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
19-7
19.3.2.2
Ethernet Physical Transceiver Control Register 1 (EPHYCTL1)
Figure 19-4. Ethernet Physical Transceiver Control Register 1 (EPHYCTL1)
19.3.2.3
Ethernet Physical Transceiver Status Register (EPHYSR)
Figure 19-5. Ethernet Physical Transceiver Status Register (EPHYSR)
IPSBAR
Offset: 0x1E_0001 (EPHYCTL1)
Access: User read/write
7
6
5
4
3
2
1
0
R
0
0
0
PHYADD4
PHYADD3
PHYADD2
PHYADD1
PHYADD0
W
Reset
0
0
0
0
0
0
0
0
Table 19-3. EPHYCTL1 Field Descriptions
Field
Description
7–5
Reserved, should be cleared.
4–0
PHYADDn
EPHY Address for MII Requests. These bits can be written anytime, but the EPHY address is latched
to the MII PHY address register (MII address 21.4:0) only when the EPHYEN bit transitions from 0 to
1. PHYADD4 is the MSB of the of the EPHY address.
IPSBAR
Offset: 0x1E_0002 (EPHYSR)
Access: User read/write
7
6
5
4
3
2
1
0
R
0
0
100DIS
10DIS
0
0
0
EPHYIF
W
Reset
0
0
1
1
0
0
0
0
Table 19-4. EPHYSR Field Descriptions
Field
Description
7–6
Reserved, should be cleared.
5
100DIS
EPHY Port 100BASE-TX mode status. This bit is not writable — i.e., read-only. Output to indicate
EPHY port Base100-TX mode status.
1 EPHY port 100BASE-TX disabled
0 EPHY port 100BASE-TX enabled
4
10DIS
EPHY Port 10BASE-T mode status.
This bit is not writable. Output to indicate EPHY port 10BASE-T mode status.
1 EPHY port 10BASE-T disabled
0 EPHY port 10BASE-T enabled
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
