Freescale Semiconductor MCF52230 ColdFire, Reference Manual

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Fast Ethernet Controller (FEC)
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 18-43
18.5.4.20 FIFO Receive Start Register (FRSR)
The FRSR is an 8-bit register programmed by the user to indicate the starting address of the receive FIFO.
FRSR marks the boundary between the transmit and receive FIFOs. The transmit FIFO uses addresses
from the start of the FIFO to the location four bytes before the address programmed into the FRSR. The
receive FIFO uses addresses from FRSR to FRBR inclusive.
The FRSR register is initialized by hardware at reset. FRSR only needs to be written to change the default
value.
IPSBAR
Offset: 0x1150 (FRSR)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0 0 0 0 0 0 R_FSTART 0 0
W
Reset 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0
Figure 18-23. FIFO Receive Start Register (FRSR)
Table 18-32. FRSR Field Description
Field Description
31–10 Reserved, read as 0 (except bit 10, which is read as 1).
9–2
R_FSTART
Address of first receive FIFO location. Acts as delimiter between receive and transmit FIFOs.
1–0 Reserved, read as 0.
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