Fast Ethernet Controller (FEC)
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
18-8
Freescale Semiconductor
the TC bit value. Following the transmission of the CRC, the Ethernet controller writes the frame status
information to the MIB block. Short frames are automatically padded by the transmit logic (if the TC bit
in the transmit buffer descriptor for the end of frame buffer equals 1).
Buffer (TXB) and frame (TFINT) interrupts may be generated as determined by the settings in the EIMR.
The transmit error interrupts are HBERR, BABT, LATE_COL, COL_RETRY_LIM, and XFIFO_UN. If
the transmit frame length exceeds MAX_FL, bytes the BABT interrupt is asserted; however, the entire
frame is transmitted (no truncation).
To pause transmission, set the GTS (graceful transmit stop) bit in the TCR register. When the TCR[GTS]
is set, the FEC transmitter stops immediately if transmission is not in progress; otherwise, it continues
transmission until the current frame finishes or terminates with a collision. After the transmitter has
stopped the GRA (graceful stop complete) interrupt is asserted. If TCR[GTS] is cleared, the FEC resumes
transmission with the next frame.
The Ethernet controller transmits bytes least significant bit first.
18.4.6.1
Duplicate Frame Transmission
The FEC fetches transmit buffer descriptors (TxBDs) and the corresponding transmit data continuously
until the transmit FIFO is full. It does not determine whether the TxBD to be fetched is already being
processed internally (as a result of a wrap). As the FEC nears the end of the transmission of one frame, it
begins to DMA the data for the next frame. To remain one BD ahead of the DMA, it also fetches the TxBD
for the next frame. The FEC can fetch from memory a BD that has already been processed but not yet
written back (it is read a second time with the R bit remaining set). In this case, the data is fetched and
transmitted again.
Using at least three TxBDs fixes this problem for large frames, but not for small frames. To ensure correct
operation for large or small frames, one of the following must be true:
•
The FEC software driver ensures that there is always at least one TxBD with the ready bit cleared.
•
Every frame uses more than one TxBD and every TxBD but the last is written back immediately
after the data is fetched.
•
The FEC software driver ensures a minimum frame size,
n
. The minimum number of TxBDs is
then (Tx FIFO Size
÷
(
n
+ 4)) rounded up to the nearest integer (though the result cannot be less
than three). The default Tx FIFO size is 192 bytes; this size is programmable.
18.4.7
FEC Frame Reception
The FEC receiver is designed to work with almost no intervention from the host and can perform address
recognition, CRC checking, short frame checking, and maximum frame length checking.
When the driver enables the FEC receiver by asserting ECR[ETHER_EN], it immediately starts
processing receive frames. When ERXDV asserts, the receiver first checks for a valid PA/SFD header. If
the PA/SFD is valid, it is stripped and the frame is processed by the receiver. If a valid PA/SFD is not found,
the frame is ignored.
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
