Freescale Semiconductor MCF52230 ColdFire, Reference Manual

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Programmable Interrupt Timers (PIT0–PIT1)
Freescale Semiconductor 22-6
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Figure 22-5. Counter Reloading from the Modulus Latch
22.3.2 Free-Running Timer Operation
This mode of operation is selected when the PCSR n [RLD] bit is clear. In this mode, the counter rolls over
from 0x0000 to 0xFFFF without reloading from the modulus latch and continues to decrement.
When the counter reaches a count of 0x0000, PCSR n [PIF] flag is set. If the PCSR n [PIE] bit is set, PIF flag
issues an interrupt request to the CPU.
When the PCSR n [OVW] bit is set, counter can be directly initialized by writing to PMR n without having
to wait for the count to reach 0x0000.
Figure 22-6. Counter in Free-Running Mode
22.3.3 Timeout Specifications
The 16-bit PIT counter and prescaler supports different timeout periods. The prescaler divides the internal
bus clock period as selected by the PCSR
n [PRE] bits. The PMR n [PM] bits select the timeout period.
Eqn. 22-1
22.3.4 Interrupt Operation
Table 22-6 shows the interrupt request generated by the PIT.
Table 22-6. PIT Interrupt Requests
Interrupt Request Flag Enable Bit
Timeout PIF PIE
0x0002 0x0001 0x0000 0x0005
0x0005
PIT Clock
Counter
Modulus
PIF
0x0002 0x0001 0x0000 0xFFFF
0x0005
PIT CLOCK
COUNTER
MODULUS
PIF
Timeout period
2
PCSRn[PRE]
(PMRn[PM] 1) +
×
f
sys/2
--------------------------------------------------------------------------
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