ColdFire Flash Module (CFM)
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
17-17
•
How to write the CFMCLKD register
•
Command write sequences used to program, erase, and verify the flash memory
•
Valid flash commands
•
Errors resulting from illegal command write sequences to the flash memory
17.4.2.3.1
Writing the CFMCLKD Register
Prior to issuing any command, it is first necessary to write the CFMCLKD register to divide the input clock
to within the 150 KHz to 200 KHz range. The CFMCLKD register bits PRDIV8 and DIV are set as
follows:
For frequencies of the input clock greater than 12.8 MHz, the CFMCLKD bit PRDIV8 must be set.
CFMCLKD DIV bit field must be chosen such that the following equation is valid:
If PRDIV8 == 1 then FCLK = input clock / 8, else FCLK = input clock
If (FCLK[KHz] / 200KHz) is integer then DIV = (FCLK[KHz] / 200KHz) - 1,
else DIV = INT (FCLK[KHz] / 200kHz)
FCLK, the clock to the flash block timing control, is therefore:
FCLK = (input clock) / (DIV + 1)
150KHz < FCLK <= 200KHz
For example, if the input clock frequency is 33 MHz, the CFMCLKD DIV field should be set to 0x14 and
bit PRDIV8 set to 1. The resulting FCLK is 196.4 KHz. As a result, the flash memory program and erase
algorithm timings are increased over the optimum target by:
(200 - 196.4) / 200 x 100% = 1.78%
Remark: INT(X) means taking the integer part of X
Example: INT(33MHz/8/200KHz) = 20
CAUTION
Programming the flash with input clock < 150 KHz should be avoided.
Setting CFMCLKD to a value such that FCLK < 150 KHz can destroy the
flash memory due to overstress. Setting CFMCLKD to a value such that
FCLK > 200 KHz can result in incomplete programming or erasure of the
flash memory array cells.
NOTE
Program and Erase command execution time increases proportionally with
the period of FCLK.
If the CFMCLKD register is written, the DIVLD bit is set automatically. If the DIVLD bit is 0, the
CFMCLKD register has not been written since the last reset. No command can be executed if the
CFMCLKD register has not been written to
Section 17.4.2.3.5, “Flash Normal Mode Illegal Operations
.”
17.4.2.3.2
Command Write Sequence
The flash command controller is used to supervise the command write sequence to execute blank check,
page erase verify, program, page erase, and mass erase algorithms.
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
