Fast Ethernet Controller (FEC)
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
18-29
a 01 pattern, and the TA field must be written with a 10. If other patterns are written to these fields, a frame
is generated but does not comply with the IEEE 802.3 MII definition.
To generate an IEEE 802.3-compliant MII Management Interface write frame (write to a PHY register),
the user must write {01 01 PHYAD REGAD 10 DATA} to the MMFR register. Writing this pattern causes
the control logic to shift out the data in the MMFR register following a preamble generated by the control
state machine. During this time, the contents of the MMFR register are altered as the contents are serially
shifted and are unpredictable if read by the user. After the write management frame operation has
completed, the MII interrupt is generated. At this time, the contents of the MMFR register match the
original value written.
To generate an MII Management Interface read frame (read a PHY register) the user must write {01 10
PHYAD REGAD 10 XXXX} to the MMFR register (the content of the DATA field is a don’t care). Writing
this pattern causes the control logic to shift out the data in the MMFR register following a preamble
generated by the control state machine. During this time, the contents of the MMFR register are altered as
the contents are serially shifted and are unpredictable if read by the user. After the read management frame
operation has completed, the MII interrupt is generated. At this time, the contents of the MMFR register
match the original value written except for the DATA field whose contents have been replaced by the value
read from the PHY register.
If the MMFR register is written while frame generation is in progress, the frame contents are altered.
Software should use the MII_STATUS register and/or the MII interrupt to avoid writing to the MMFR
register while frame generation is in progress.
18.5.4.7
MII Speed Control Register (MSCR)
The MSCR provides control of the MII clock (EMDC pin) frequency, allows a preamble drop on the MII
management frame, and provides observability (intended for manufacturing test) of an internal counter
used in generating the EMDC clock signal.
IPSBAR
Offset: 0x1044 (MSCR)
Access: User read/write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
DIS_
PREA
MBLE
MII_SPEED
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
