Fast Ethernet Controller (FEC)
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
18-35
18.5.4.12 Physical Address High Register (PAUR)
The PAUR is written by the user. This register contains the upper 16 bits (bytes 4 and 5) of the 48-bit
address used in the address recognition process to compare with the DA (destination address) field of
receive frames with an individual DA. In addition, this register is used in bytes 4 and 5 of the 6-byte Source
Address field when transmitting PAUSE frames. Bits 15:0 of PAUR contain a constant type field (0x8808)
used for transmission of PAUSE frames. This register is not reset and bits 31:16 must be initialized by the
user.
IPSBAR
Offset: 0x10E8 (PAUR)
Access: User read/write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
PADDR2
W
Reset
Undefined
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
TYPE
W
Reset
1
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
Figure 18-15. Physical Address High Register (PAUR)
Table 18-24. PAUR Field Descriptions
Field
Description
31–16
PADDR2
Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address to be used for exact match,
and the Source Address field in PAUSE frames.
15–0
TYPE
Type field in PAUSE frames. These 16 bits are a constant value of 0x8808.
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
