Freescale Semiconductor MCF52230 ColdFire, Reference Manual

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Fast Ethernet Controller (FEC)
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
18-6 Freescale Semiconductor
18.4.3 Microcontroller Initialization
In the FEC, the descriptor control RISC initializes some registers after ECR[ETHER_EN] is asserted.
After the microcontroller initialization sequence is complete, the hardware is ready for operation.
Table 18-4 shows microcontroller initialization operations.
18.4.4 User Initialization (After Asserting ECR[ETHER_EN])
After asserting ECR[ETHER_EN], the user can set up the buffer/frame descriptors and write to the TDAR
and RDAR. Refer to
Section 18.6, “Buffer Descriptors ” for more details.
18.4.5 Network Interface Options
The FEC supports an MII interface for 10/100 Mbps Ethernet and a 7-wire serial interface for 10 Mbps
Ethernet. The interface mode is selected by the RCR[MII_MODE] bit. In MII mode
(RCR[MII_MODE] = 1), there are 18 signals defined by the IEEE 802.3 standard and supported by the
EMAC. These signals are shown in
Table 18-5 below.
Table 18-4. Microcontroller Initialization
Description
Initialize BackOff Random Number Seed
Activate Receiver
Activate Transmitter
Clear Transmit FIFO
Clear Receive FIFO
Initialize Transmit Ring Pointer
Initialize Receive Ring Pointer
Initialize FIFO Count Registers
Table 18-5. MII Mode
Signal Description EMAC pin
Transmit Clock ETXCLK
Transmit Enable ETXEN
Transmit Data ETXD[3:0]
Transmit Error ETXER
Collision ECOL
Carrier Sense ECRS
Receive Clock ERXCLK
Receive Data Valid ERXDV
Receive Data ERXD[3:0]
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