Fast Ethernet Controller (FEC)
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
18-9
In serial mode, the first 16 bit times of RX_D0 following assertion of ERXDV are ignored. Following the
first 16 bit times the data sequence is checked for alternating 1/0s. If a 11 or 00 data sequence is detected
during bit times 17 to 21, the remainder of the frame is ignored. After bit time 21, the data sequence is
monitored for a valid SFD (11). If a 00 is detected, the frame is rejected. When a 11 is detected, the PA/SFD
sequence is complete.
In MII mode, the receiver checks for at least one byte matching the SFD. Zero or more PA bytes may occur,
but if a 00 bit sequence is detected prior to the SFD byte, the frame is ignored.
After the first 6 bytes of the frame have been received, the FEC performs address recognition on the frame.
After a collision window (64 bytes) of data has been received and if address recognition has not rejected
the frame, the receive FIFO is signalled that the frame is accepted and may be passed on to the DMA. If
the frame is a runt (due to collision) or is rejected by address recognition, the receive FIFO is notified to
reject the frame. Thus, no collision fragments are presented to the user except late collisions, which
indicate serious LAN problems.
During reception, the Ethernet controller checks for various error conditions and after the entire frame is
written into the FIFO, a 32-bit frame status word is written into the FIFO. This status word contains the
M, BC, MC, LG, NO, CR, OV and TR status bits, and the frame length. See
” for more details.
Receive Buffer (RXB) and Frame Interrupts (RFINT) may be generated if enabled by the EIMR register.
A receive error interrupt is babbling receiver error (BABR). Receive frames are not truncated if they
exceed the max frame length (MAX_FL); however, the BABR interrupt occurs and the LG bit in the
Receive Buffer Descriptor (RxBD) is set. See
Section 18.6.2, “Ethernet Receive Buffer Descriptor
” for more details.
When the receive frame is complete, the FEC sets the L-bit in the RxBD, writes the other frame status bits
into the RxBD, and clears the E-bit. The Ethernet controller next generates a maskable interrupt (RFINT
bit in EIR, maskable by RFIEN bit in EIMR), indicating that a frame has been received and is in memory.
The Ethernet controller then waits for a new frame.
The Ethernet controller receives serial data LSB first.
18.4.8
Ethernet Address Recognition
The FEC filters the received frames based on destination address (DA) type — individual (unicast), group
(multicast), or broadcast (all-ones group address). The difference between an individual address and a
group address is determined by the I/G bit in the destination address field. A flowchart for address
recognition on received frames is illustrated in the figures below.
Address recognition is accomplished through the use of the receive block and microcode running on the
microcontroller. The flowchart shown in
illustrates the address recognition decisions made by
illustrates the decisions made by the microcontroller.
If the DA is a broadcast address and broadcast reject (RCR[BC_REJ]) is deasserted, then the frame is
accepted unconditionally, as shown in
. Otherwise, if the DA is not a broadcast address, then
the microcontroller runs the address recognition subroutine, as shown in
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
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available
from
Freescale
for
import
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sale
in
the
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States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
