Ethernet Physical Transceiver (EPHY)
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
19-32
Freescale Semiconductor
19.4.5.2
Wait Mode
If the MCU executes a WAIT instruction with the EPHYWAI bit set, the EPHY is powered down and all
internal MII registers reset to their default state. Upon exiting STOP mode the EPHY exits the power-down
state and latch the values previously written to the EPHYCTL0 and EPHYCTL1 registers. The MII
registers must be re-initialized after the start-up delay (t
Start-up
) has expired.
19.4.5.3
MII Power Down
This mode disconnects the PHY from the network interface (three-state receiver and driver pins).
Setting bit 0.11 of the port enters this mode. In this mode, the management interface is accessible but all
internal chip functions are in a zero power state.
In this mode all analog blocks except the PLL clock generator and band gap reference are in low power
mode. All digital blocks except the MDIO interface and management registers are inactive.
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
