Freescale Semiconductor MCF52230 ColdFire, Reference Manual

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Fast Ethernet Controller (FEC)
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
18-2 Freescale Semiconductor
18.2.1 Full and Half Duplex Operation
Full duplex mode is intended for use on point to point links between switches or end node to switch. Half
duplex mode is used in connections between an end node and a repeater or between repeaters. Selection
of the duplex mode is controlled by TCR[FDEN].
When configured for full duplex mode, flow control may be enabled. Refer to the TCR[RFC_PAUSE] and
TCR[TFC_PAUSE] bits, the RCR[FCE] bit, and
Section 18.4.10, “Full Duplex Flow Control ,” for more
details.
18.2.2 Interface Options
The following interface options are supported. A detailed discussion of the interface configurations is
provided in
Section 18.4.5, “Network Interface Options ”.
18.2.2.1 10 Mbps and 100 Mbps MII Interface
MII is the Media Independent Interface defined by the IEEE 802.3 standard for 10/100 Mbps operation.
The MAC-PHY interface may be configured to operate in MII mode by asserting RCR[MII_MODE].
The speed of operation is determined by the ETXCLK and ERXCLK pins which are driven by the external
transceiver. The transceiver auto-negotiates the speed or it may be controlled by software via the serial
management interface (EMDC/EMDIO pins) to the transceiver. Refer to the MMFR and MSCR register
descriptions as well as the section on the MII for a description of how to read and write registers in the
transceiver via this interface.
18.2.3 Address Recognition Options
The address options supported are promiscuous, broadcast reject, individual address (hash or exact match),
and multicast hash match. Address recognition options are discussed in detail in
Section 18.4.8, “Ethernet
Address Recognition ”.
18.2.4 Internal Loopback
Internal loopback mode is selected via RCR[LOOP]. Loopback mode is discussed in detail in
Section 18.4.13, “Internal and External Loopback ”.
18.3 FEC Top-Level Functional Diagram
The block diagram of the FEC is shown below. The FEC is implemented with a combination of hardware
and microcode. The off-chip (Ethernet) interfaces are compliant with industry and IEEE 802.3 standards.
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60