Freescale Semiconductor MCF52230 ColdFire, Reference Manual

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System Control Module (SCM)
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor 13-15
Only trusted bus masters can modify the access control registers. If a non-trusted bus master attempts to
write any of the SACU control registers, the access is aborted with an error termination and the registers
remain unaffected.
The processor core is connected to bus master 0 and is always treated as a trusted bus master. Accordingly,
MPR[0] is forced to 1 at reset.
13.7.3.2 Peripheral Access Control Registers (PACR0–PACR9)
Access to several on-chip peripherals is controlled by shared peripheral access control registers. A single
PACR defines the access level for each of the two modules. These modules only support operand reads
and writes. Each PACR follows the format illustrated in
Figure 13-9 . For a list of PACRs and the modules
that they control, refer to Table 13-11 .
Table 13-8. MPR[n] Field Descriptions
Field Description
7–4 Reserved. Should be cleared.
3–0
MPR
Each 1-bit field defines the access privilege level of the given bus master n.
0 All bus master accesses are in user mode.
1 All bus master accesses use the sourced user/supervisor attribute.
IPSBAR
Offset: Offset
1
(PACRn)
1
See Table 13-1 for the full list of addresses.
Access: read/write
7 6 5 4 3 2 1 0
R
LOCK1 ACCESS_CTRL1 LOCK0 ACCESS_CTRL0
W
Reset: 0 0 0 0 0 0 0 0
Figure 13-9. Peripheral Access Control Register (PACRn)
Table 13-9. PACR Field Descriptions
Field Description
7
LOCK1
This bit, when set, prevents subsequent writes to ACCESSCTRL1. Any attempted write to the PACR
generates an error termination and the contents of the register are not affected. Only a system reset clears
this flag.
6–4
ACCESS_CTRL1
This 3-bit field defines the access control for the given platform peripheral.
The encodings for this field are shown in
Table 13-10 .
3
LOCK0
This bit, when set, prevents subsequent writes to ACCESSCTRL0. Any attempted write to the PACR
generates an error termination and the contents of the register are not affected. Only a system reset clears
this flag.
2–0
ACCESS_CTRL0
This 3-bit field defines the access control for the given platform peripheral.
The encodings for this field are shown in
Table 13-10 .
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