Embedded Solutions
Page 69 of 71
Specifications
PCIe Interfaces:
PCIe 1 lane (x1) interface
Access types:
Configuration and Memory space utilized
CLK rates supported:
Standard 100 MHz PCI Express differential reference clock for PCIe interface. IP
interface clock run at either 8MHz or 32MHz.
Memory
Multiple FIFO’s are implemented to support multiple parallel processes at any
one time within the Lattice FPGA’s. Parallel processing is achieved with IP
accesses. Controllable for sequenced IO across multiple IP’s.
IO
Level shifters are used to shift 3.3V FPGA signaling to 5.0V IP signaling.
Interface:
50 pin header. Right angle through the bezel for position 0 and vertical headers
for positions 1 and 2 for PCIe3IP or positions 1, 2, 3, 4 for PCIe5IP. Bezel has
special features for routing rear connector cables through the bezel. VPX2IP - 3U
4HP with bezel or VPX connector/rear IO with blank bezel. Comes with alignment
pins, and mounting screws.
Software Interface:
Control Registers within Lattice FPGA. Drivers provide generic calls for GPB
access to allow any user modification to be programmed with the standard driver.
Initialization:
Programming procedure documented in this manual
Access Modes:
Registers on long/double word boundaries. Standard target access read and
write to registers and memory.
Access Time:
Programmable time-out for IP Bus Error situations
.
Interrupt:
1 interrupt is supported with multiple sources. The interrupts are maskable and
are supported with a status and control registers.
Onboard Options:
Selectable shunt for 3.3V or 5V reference Bus Termination
Board Stuffing Options:
PCIe3IP only - Resistor stuffing options to reconfigure the connectivity between
IP1 and IP2’s carrier I/O SMT and 50 pin headers
VPX2IP only - Resistor stuffing options to reconfigure the connectivity between
IP0 and IP1’s carrier I/O SMT and 50 pin Condo header or VPX connector.
Dimensions:
VPX2IP - 3U 4HP with bezel or VPX connector/rear IO with blank bezel.
PCIe3IP - half-length PCIe board.
PCIe5IP - full-length PCIe board.
Construction:
High Temp FR4 Multi-Layer Printed Circuit, Surface Mount Components.
Power:
12V and 3.3V from PCIe bus. Local 5V, 3.3V, 1.2V, and -12V created
with on-board power supplies.
