Embedded Solutions
Page 59 of 71
PCIe5IP Board Features
PCIe5IP DIP Switches
There are two DIP Switches on PCIe5IP, each with 8 switches. They are labeled SW1
and SW2 with bit numbers 7 to 0 and O/C for Open/Closed in the silk screen.
O
7
0
C
SW1 is for user purposes. The settings of SW1 can be seen/used by reading the Switch
and LED register [7:0] bits which correspond to SW1 [7:0] bit positions. When a switch
is in the C/Closed position the bit value read is 0, when in the O/Open position the value
read is 1. Switch values can also be displayed on LED[7:0] by setting the LED Select
value (Switch and LED register bits [27:24]) = 0010.
SW2 bits configure PCIe5IP (see Switch and LED register for details) as follows:
o
SW2 [7:6] bit positions select the Flash image to be used to configure the FPGA
at power up and can be read by reading the Switch and LED register [13:12] bits.
o
SW2 [5] is used to configure logic inside the FPGA. This switch setting can be
seen by reading the Switch and LED register bit [8].
o
SW2 [4:0] selects either 5.0V or 3.3V to be the Bus Termination voltage for each
IP. SW2 [4:0] corresponds one to one with IP [4:0] Bus Termination voltage
selection. When the switch is in the closed position (logic 0) a FET is turned on
resulting in 5V referenced logic. When the switch is in the open position (logic 1)
the FET is disabled and the logic reference is 3.3V. The ES[4:0]V pads on the
board can be checked with a multi-meter to make sure you have the expected
bus reference/termination voltage. The PCIe5IP ships with SW2[4:0] = 00000, all
IP set to operate with 5V signaling/bus termination. Please note: The 3.3V
reference is provided through a blocking diode which results in a small voltage
drop.
