Embedded Solutions
Page 41 of 71
Interrupt Control Register (ICR) – Offset 0x00C
Bit(s)
Description
Attribute Default
31:14
Reserved
RO
0h
13
Interrupt Aggregation enable
0 = Interrupt Aggregation off, Interrupt Aggregation timer &
logic disabled. Interrupts will be generated upon occurrence,
or after the Interrupt de-assert time has expired (time relative
to the last de-assertion).
1 = Interrupt Aggregation on, Interrupt Aggregation timer &
logic enabled.
R/W
0h
12
Reserved
RO
0h
11:8
Interrupt Aggregation Timer
These bits set the Interrupt Aggregation timer, i.e. the rate or
pace at which an interrupt (INTA# or MSI) may generated and
sent to the Host. An MSI or INTA# assert packet is sent if an
interrupt in the ISR (0x008) is set and the Interrupt
Aggregation logic is enabled when this timer expires. INTA#
de-assert packets are sent upon W1C of ISR occurrence.
0000 = 32us 0100 = 512us 1000 = 8ms 1100 = 128ms
0001 = 64us 0101 = 1ms 1001 = 16ms 1101 = 256ms
0010 = 128us 0110 = 2ms 1010 = 32ms 1110 = 512ms
0011 = 256us 0111 = 4ms 1011 = 64ms 1111 = 1Sec
R/W
0h
7:3
Reserved
RO
0h
2:0
Interrupt de-assert time
Minimum time delay from an interrupt (INTA# or MSI) de-
assertion to interrupt assertion. An interrupt assertion
following a de-assertion in the minimum time may be caused
by:
The interrupt source for the previous interrupt is still
asserted when the W1C of the ISR, to clear it, is
executed.
Multiple Interrupts are asserted, but not all are W1C.
A new/different interrupt occurs while (or after) the
W1C Interrupt Status register (0x008) bit or bits are
cleared.
Note: Delays are approximate due to clock synchronization
delays.
000 = 96ns (IPCLK = 32Mhz) or 288ns (IPCLK = 8MHz).
001 = 544ns
010 = 1.06us
011 = 2.08us
100 = 4.13us
101 = 8.22us
110 = 16.42us
111 = 32.67us
R/W
0h
